参数资料
型号: DS3170DK
厂商: Maxim Integrated Products
文件页数: 11/40页
文件大小: 0K
描述: KIT DESIGN FOR DS3170
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
设计资源: DS3170DK Gerber Files
标准包装: 1
主要目的: 电信,调帧器和线路接口装置(LIU)
已用 IC / 零件: DS3170
已供物品: 板,CD
DS3170DK DS3/E3 Single-Chip Transceiver Design Kit
CONTROL REGISTERS
Register Name: CTRL1
Register Description: Control Register 1
Register Offset: 0x0008
Bit #
Name
Default
7
SPI_CPOL
0
6
SPI_CPHA
0
5
SPI_SWAP
0
4
SPI
0
3
HIZ
1
2
WIDTH
0
1
MOT
0
0
MUX
0
Bit 7: SPI_CPOL:
Bit 6: SPI_CPHA:
Bit 5: SPI_SWAP:
Bit 4: SPI:
Bit 3: HIZ:
Bit 2: WIDTH:
Bit 1: MOT:
Bit 0: MUX:
This bit controls the SPI Interface Clock Polarity pin, which is muxed with the D7 pin on the
DS3170. Bit 7 is only active when bit 4 (SPI) is a logic 1. Refer to the DS3170 data sheet
for pin operation.
This bit controls the SPI Interface Clock Phase pin, which is muxed with the D6 pin on the
DS3170. Bit 6 is only active when Bit 4 (SPI) is a logic 1. Refer to the DS3170 data sheet
for pin operation.
This bit controls the SPI Interface Bit Order Swap pin, which is muxed with the D5 pin on
the DS3170. Bit 5 is only active when Bit 4 (SPI) is a logic 1. Refer to the DS3170 data
sheet for pin operation.
This bit controls the SPI Bus Mode bit.
0 = parallel bus mode
1 = SPI bus mode
This bit controls the high-impedance test-enable bit (active low). This signal puts all the
digial outputs and bidirectional outputs to a high-impedance state when pulled low and
also when the JTRST is pulled low. For nomal operation, keep it as a logic 1.
This bit controls the databus width pin for parallel bus mode.
0 = 8-bit parallel mode
1 = 16-bit parallel mode
This bit controls the MODE pin for the DS3170.
0 = RD/WR strobe mode (Intel)
1 = DS strobe mode (Motorola)
This bit determines if the ALE pin on the DS3170 is in mux mode or nonmux mode
(constantly high).
0 = nonmux mode
1 = mux mode
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