参数资料
型号: DS3170DK
厂商: Maxim Integrated Products
文件页数: 5/40页
文件大小: 0K
描述: KIT DESIGN FOR DS3170
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
设计资源: DS3170DK Gerber Files
标准包装: 1
主要目的: 电信,调帧器和线路接口装置(LIU)
已用 IC / 零件: DS3170
已供物品: 板,CD
DS3170DK DS3/E3 Single-Chip Transceiver Design Kit
BASIC OPERATION
This design kit relies upon several supporting files, which are available for downloading on our website at
www.maxim-ic.com/telecom . See the DS3170DK QuickView page for files.
The support files are used with an evaluation program called ChipView with is available for download at
HARDWARE CONFIGURATION
Quick Start (Hardware Settings)
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For single power-supply operation, short jumpers JP1-JP3. This connects VDD of the DS3170 to the board
VCC.
Ensure that PROGRAM FLASH MICRO is selected (SW6). DS3 should not be on.
Connect reference clock. See Table 1 .
DIP switches (SW3) can be in either the ON or OFF position depending on the desired configuration. See
Connect serial cable from DS3170DK (J2) to PC.
Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V.
Reference Clock Configuration
The reference clock for the DS3170 (SCT) can be configured a number of ways depending on the application's
need. This is done by shorting the REFCLK signal on J6 to the signal inputs, which are also connected to J6.
Table 1: Reference Clock Configuration
REFERENCE
CLOCK
GND
BNC Input
STS1 OSC
E3 OSC
T3 OSC
DESCRIPTION
Short pins J6.1 and J6.2 together. Open all other pins on J6.
Short pins J6.3 and J6.4 together. Open all other pins on J6.
Short pins J6.5 and J6.6 together. Open all other pins on J6.
Short pins J6.7 and J6.8 together. Open all other pins on J6.
Short pins J6.9 and J6.10 together. Open all other pins on J6.
JTAG Configuration
The JTAG chain is controlled by the following connectors: J4, JP4, and JP5. Depending on the function, such as
programming the internal microcontroller flash or performing boundary scan operations, the three connectors can
be configured to accomplish the desired task. For information on programming the internal flash of the
microcontroller, refer to the microcontroller user manual and board schematic.
For most purposes, having the complete JTAG chain is sufficient. Figure 1 shows the complete chain as well as
what order the devices will appear during boundary scan. To set up this configuration, perform the following:
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Connect JTDI to JP4.1
Connect JTDO to JP4.3
Connect JTMS to JP4.10
Connect JCLK to JP4.5
Connect J4.1 to J4.2
Connect J4.3 to J4.4
Connect JP5.1 to JP5.2
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