参数资料
| 型号： | DS32C35-33IND# |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 10/22页 |
| 文件大小： | 0K |
| 描述： | IC RTC W/TCXO 20-SOIC |
| 产品变化通告： | Product Discontinuation 28/Nov/2011 |
| 标准包装： | 37 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，FRAM，闰年，方波输出，TCXO/晶体 |
| 存储容量： | 8KB |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.7 V ~ 3.63 V |
| 电压 - 电源，电池： | 2.3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 管件 |
| 产品目录页面： | 1433 (CN2011-ZH PDF) |
DS32B35/DS32C35
Accurate I2C RTC with Integrated
TCXO/Crystal/FRAM
18
____________________________________________________________________
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain
high.
Start data transfer: A change in the state of the
data line from high to low, while the clock line is high,
defines a START condition.
Stop data transfer: A change in the state of the data
line from low to high, while the clock line is high,
defines a STOP condition.
Data valid: The state of the data line represents
valid data when, after a START condition, the data
line is stable for the duration of the high period of the
clock signal. The data on the line must be changed
during the low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number
of data bytes transferred between the START and
the STOP conditions is not limited, and is determined
by the master device. The information is transferred
byte-wise and each receiver acknowledges with a
ninth bit.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device
must generate an extra clock pulse, which is associ-
ated with this acknowledge bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
Depending upon the state of the R/W bit, two types of
data transfer are possible:
1) Data transfer from a master transmitter to a
slave receiver. The first byte transmitted by the
master is the slave address. Next follows a num-
ber of data bytes. The slave returns an acknowl-
edge bit after each received byte. Data is
transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a
master receiver. The first byte (the slave
address) is transmitted by the master. The slave
then returns an acknowledge bit. Next follows a
number of data bytes transmitted by the slave to
the master. The master returns an acknowledge
bit after all received bytes other than the last byte.
At the end of the last received byte, a not
acknowledge is returned.
The master device generates all the serial clock
pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a
repeated START condition. Since a repeated
START condition is also the beginning of the next
serial transfer, the bus will not be released. Data
is transferred with the most significant bit (MSB)
first.
The DS32B35/DS32C35 can operate in the following two
modes:
1) Slave receiver mode (DS32B35/DS32C35 write
mode): Serial data and clock are received through
SDA and SCL. After each byte is received an
acknowledge bit is transmitted. START and STOP
conditions are recognized as the beginning and end
of a serial transfer. Address recognition is performed
by hardware after reception of the slave address
and direction bit (see Figures 3, 5, and 7). The slave
address byte is the first byte received after the mas-
ter generates the START condition. The slave
address byte contains one of the 7-bit device
addresses. The slave address is 1101000 for the
RTC. For the DS32B35 FRAM, the first four bits are
1010, and the next three bits select one of eight
blocks of data (see Table 2). For the DS32C35
FRAM, the first seven bits are 1010000. Each slave
address is followed by the direction bit (R/W), which
is zero for a write. After receiving and decoding the
slave address byte, the device outputs an acknowl-
edge on the SDA line. After the device acknowl-
edges the slave address and write bit, the master
transmits a register address to the device. For the
DS32C35, the master transmits two bytes for the
register address information. This sets the register
pointer on the device. After setting the register
address, the master then transmits zero or more
bytes of data with the device acknowledging each
byte received. The master generates a STOP condi-
tion to terminate the data write.
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相关代理商/技术参数 |
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| DS32C35-33IND# | 功能描述:实时时钟 w/Integrated TCXO/Crystal/FRAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| DS32EL0124 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:125 MHz . 312.5 MHz Deserializer with DDR LVDS Parallel Interface |
| DS32EL0124_0807 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:125 MHz . 312.5 MHz Deserializer with DDR LVDS Parallel Interface |
| DS32EL0124_09 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface |
| DS32EL0124SQ | 制造商:NSC 制造商全称:National Semiconductor 功能描述:125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface |
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