参数资料
| 型号： | DS33Z41DK |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 12/44页 |
| 文件大小： | 0K |
| 描述： | KIT DESIGN FOR DS33Z41 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 主要目的： | 接口，以太网 |
| 已用 IC / 零件： | DS33Z41 |
| 已供物品： | 板，串行卡，CD |
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DS33Z41DK
CONFIGURATION SWITCHES AND JUMPERS
The DS33Z41DK has several configuration switches, banana plugs, oscillators, and jumpers. Table 2 provides a
description of these signals, given in order of appearance on the PC board (going from left to right, top to bottom).
Table 2. Main Board PC Board Configuration
SILKSCREEN
REFERENCE
FUNCTION
BASIC SETTING
SW MODE HW MODE
DESCRIPTION
This jumper is not for use with
J45.9 + J45.10
Reserved
Not installed
—
the DS33Z41 design kit. Pin
J25.10 has been removed to
prevent accidental installation
When installed the device driver
J45.7 + J45.8
Enable device driver
User decision
—
will configure the DS33Z41 and
the Transceiver during power-up.
J45.5 + J45.6
Enable callbacks
User decision
—
When installed the driver will
respond to interrupts
When installed the driver will
configure DS21458 TCLK to be
sourced from DS21458 RCLK.
J45.3 + J45.4
Select TCLK source
User decision
—
When not installed DS21458
scaled MCLK is used. This
setting is only applied at reset. If
only one board is used select
TCLK = MCLK.
GROUND
(banana plug)
VDD 3.3V
(banana plug)
OnCe
DCEDTES
(3pos switch)
RMIIMII
(3pos switch)
CKPHA
(3pos switch)
MODEC0
(3pos switch)
MODEC1
(3pos switch)
HWMODE
(3pos switch)
SCANMO
(3pos switch)
SCANTRI
(3pos switch)
….testpoints….
Z-RESET (button)
A2, A1, A0
(3pos switches)
SDRAM CLOCK
MII CLOCK
Power supply ground
Power supply VDD
BDM
DS33Z41 mode pin;
DTE/DCE selection
DS33Z41 mode pin
DS33Z41 mode pin
DS33Z41 mode pin
DS33Z41 mode pin
DS33Z41 mode pin
DS33Z41 mode pin
DS33Z41 mode pin
DS33Z41 testpoints
DS33Z41 reset
DS33Z41/SPI pins
DS33Z41 SDRAM
clock
PHY MII clock
—
—
—
LOW
LOW
LOW
HIGH
LOW
LOW
LOW
LOW
—
—
Mid position
Installed
Installed
—
—
—
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
—
—
Mid position
Installed
Installed
System Ground. Always
connected to power supply.
System VDD. Always connected
to power supply.
Debug connector for processor
Low for DTE
High for RMII, low for MII
SPI EEPROM hardware mode
configuration switch
Software mode selected
Software mode selected
Hardware/software mode
(software mode selected)
Set low for normal operation
Set low for normal operation
Processor bus, JTAG and LAN
side testpoints for Zchip
System reset
Address pin/EEPROM config
switch. Set to mid position to
allow connection to processor.
100MHz oscillator to drive
SDRAM clock
25MHz oscillator to drive SDRAM
clock
12 of 44
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