参数资料
型号: DS33Z41DK
厂商: Maxim Integrated Products
文件页数: 14/44页
文件大小: 0K
描述: KIT DESIGN FOR DS33Z41
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: 接口,以太网
已用 IC / 零件: DS33Z41
已供物品: 板,串行卡,CD

DS33Z41DK
ADDRESS MAP (ALL CARDS)
Motorola resource card address space begins at 0x81000000. All offsets given below are relative to the beginning
of the daughter card address space (shown previously).
Table 3. Overview of Daughter Card Address Map
OFFSET
0X0000 to
0X0087
0X1000 to
0X1FFF
0X2000 to
0X2FFF
0X4000 to
0X4010
DEVICE
FPGA
DS33Z41
DS21458
FPGA
DESCRIPTION
Processor board identification
DS33Z41. Uses CS_X1.
T1/E1 DS21458 resource card. Uses CS_X2.
FPGA on DS21458 resource card. Used to facilitate IBO mode.
Default configuration of FPGA is compatible with non-IBO mode
functionality. The FPGA settings will require modification for use
with the DS33Z41 when device drivers are disabled.
Registers in the DS33Z41 and DS21458 can be easily modified using the ChipView host-based user-interface
software with the definition files previously mentioned.
Quad T1/E1 Resource Card FPGA Register Map
Table 4. Quad T1/E1 Processor Card FPGA Register Map
OFFSET
0X4000
0X4001
0X4002
0X4003
0X4004
0X4005
0X4006
0X4007
REGISTER
NAME
Rev
delay_line1
delay_line2
delay_line3
delay_line4
MO+CLK
UNUSED
UNUSED
TYPE
Read only
Control
Control
Control
Control
Control
Control
Control
DESCRIPTION
FPGA Rev
Line 1 number of frame delay
Line 2 number of frame delay
Line 3 number of frame delay
Line 4 number of frame delay
Mode and clock ctrl
Unused / test
Unused / test
ID REGISTERS
REV: FPGA REV (Offset=0X4000)
FPGA Rev is read only, showing the current FPGA revision
14 of 44
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