参数资料
型号: DS3510T+
厂商: Maxim Integrated Products
文件页数: 6/17页
文件大小: 0K
描述: IC I2C GAMMA/VCOM BUFF 48-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 209
应用: TFT-LCD 面板:伽玛缓冲器,VCOM 驱动器
输出类型: 满摆幅
电路数: 10
电流 - 电源: 6.7mA
电流 - 输出 / 通道: 4mA
电压 - 电源,单路/双路(±): 9 V ~ 15 V
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(7x7)
包装: 管件
DS3510
I2C Gamma and VCOM Buffer with EEPROM
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers. (See Figure 4 and
I2C Electrical
Characteristics for additional information.)
Master device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave devices: Slave devices send and receive data at
the master’s request.
Bus idle or not busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states.
START condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition.
STOP condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition.
Repeated START condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a
specific memory address to begin a data transfer. A
repeated START condition is issued identically to a nor-
mal START condition.
Bit write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements. Data is shifted into the
device during the rising edge of the SCL.
Bit read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA
at the falling edge of the previous SCL pulse and the
data bit is valid at the rising edge of the current SCL
pulse. Remember that the master generates all SCL
clock pulses, including when it is reading bits from the
slave.
Acknowledge (ACK and NACK): An Acknowledge
(ACK) or Not Acknowledge (NACK) is always the 9th bit
transmitted during a byte transfer. The device receiving
data (the master during a read or the slave during a
write operation) performs an ACK by transmitting a 0
during the 9th bit. A device performs a NACK by trans-
mitting a 1 during the 9th bit. Timing for the ACK and
NACK is identical to all other bit writes. An ACK is the
acknowledgment that the device is properly receiving
data. A NACK is used to terminate a read sequence or
indicates that the device is not receiving data.
CONTROL REGISTER 60h: Control Register (CR)
FACTORY DEFAULT
10h
MEMORY TYPE
NV
60h
x
BIAS1
BIAS0
x
MODE1
MODE0
bit7
bit0
bit7:6
Reserved
bit5:4
VCOM and Gamma Bias Current Control Bits:
00 = 150%
01 = 100% (default)
10 = 80%
11 = 60%
bits3:2
Reserved
bits1:0
DS3510 Mode:
00 = S0/S1 Pins are Used to Select the Desired Bank (A–D) (Default)
01 = Soft S0/S1 (Bits) Are Used to Select the Desired Bank (A–D)
1X = Latch A Is Used to Control the DACs
14
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