- 您现在的位置：买卖IC网 > PDF目录19309 > DS3881E+T&R/C (Maxim Integrated)IC AUTO CCFL CTRLR 1CH 24-TSSOP PDF资料下载
参数资料
| 型号： | DS3881E+T&R/C |
| 厂商： | Maxim Integrated |
| 文件页数： | 24/28页 |
| 文件大小： | 0K |
| 描述： | IC AUTO CCFL CTRLR 1CH 24-TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 类型： | CCFL 控制器 |
| 频率： | 40 ~ 100 kHz |
| 电流 - 电源： | 12mA |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页当前第24页第25页第26页第27页第28页
Single-Channel Automotive CCFL Controller
I 2 C Definitions
The following terminology is commonly used to
describe I 2 C data transfers:
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, start, and stop conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic-high states.
Start Condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See the timing dia-
gram for applicable timing.
Stop Condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high gener-
ates a stop condition. See the timing diagram for
applicable timing.
Repeated Start Condition: The master can use a
repeated start condition at the end of one data transfer
to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a
specific memory address to begin a data transfer. A
repeated start condition is issued identically to a nor-
mal start condition. See the timing diagram for applica-
ble timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements (see Figure 9). Data is
shifted into the device during the rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time (see Figure 9) before the next rising edge of
SCL during a bit read. The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master gener-
ates all SCL clock pulses including when it is reading
bits from the slave.
Acknowledgement (ACK and NACK): An acknowl-
edgement (ACK) or not acknowledge (NACK) is always
the 9th bit transmitted during a byte transfer. The
device receiving data (the master during a read or the
slave during a write operation) performs an ACK by
transmitting a zero during the 9th bit. A device per-
forms a NACK by transmitting a one during the 9th bit.
Timing (Figure 9) for the ACK and NACK is identical to
all other bit writes. An ACK is the acknowledgment that
the device is properly receiving data. A NACK is used
to terminate a read sequence or as an indication that
the device is not receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit-write definition and the
acknowledgement is read using the bit-read definition.
SDA
t BUF
t HD:STA
t SP
SCL
t LOW
t R
t F
t HD:STA
t HIGH
t SU:STA
STOP
START
t SU:DAT
REPEATED
START
t SU:STO
t HD:DAT
NOTE: TIMING IS REFERENCE TO V IL(MAX) AND V IH(MIN) .
Figure 9. I 2 C Timing Diagram
24
____________________________________________________________________
相关PDF资料 |
PDF描述 |
|---|---|
| VI-212-EU | CONVERTER MOD DC/DC 15V 200W |
| RMM28DTAD | CONN EDGECARD 56POS R/A .156 SLD |
| VE-B1B-CV-F4 | CONVERTER MOD DC/DC 95V 150W |
| GEM08DSXS | CONN EDGECARD 16POS DIP .156 SLD |
| VE-B1B-CV-F3 | CONVERTER MOD DC/DC 95V 150W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3882 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Dual-Channel Automotive CCFL Controller |
| DS3882_10 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Dual-Channel Automotive CCFL Controller |
| DS3882E | 制造商:Maxim Integrated Products 功能描述:CAR DUAL CCFL CONTROL TSSOP - 28 - Rail/Tube |
| DS3882E/T&R | 制造商:Maxim Integrated Products 功能描述:CAR DUAL CCFL CTRL TSSOP-28 T&R - Tape and Reel |
| DS3882E+ | 功能描述:IC CCFL CNTRLR DUAL 28TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 照明，镇流器控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:CCFL 控制器 频率:40 ~ 80 kHz 电流 - 电源:5mA 电流 - 输出:- 电源电压:4.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:16-SOIC（0.154"，3.90mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) 其它名称:90-3991V+V01 |
发布紧急采购，3分钟左右您将得到回复。