参数资料
型号: DS3881E+T&R/C
厂商: Maxim Integrated
文件页数: 4/28页
文件大小: 0K
描述: IC AUTO CCFL CTRLR 1CH 24-TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1,000
类型: CCFL 控制器
频率: 40 ~ 100 kHz
电流 - 电源: 12mA
电源电压: 4.75 V ~ 5.25 V
工作温度: -40°C ~ 105°C
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 带卷 (TR)
Single-Channel Automotive CCFL Controller
I 2 C AC ELECTRICAL CHARACTERISTICS (See Figure 9)
(V CC = +4.75V to +5.25V, T A = -40°C to +105°C, timing referenced to V IL(MAX) and V IH(MIN) .)
PARAMETER
SCL Clock Frequency
SYMBOL
f SCL
(Note 7)
CONDITIONS
MIN
0
TYP
MAX
400
UNITS
kHz
Bus Free Time Between Stop and
Start Conditions
t BUF
1.3
μs
Hold Time (Repeated) Start
Condition
Low Period of SCL
High Period of SCL
t HD:STA
t LOW
t HIGH
(Note 8)
0.6
1.3
0.6
μs
μs
μs
Data Hold Time
Data Setup Time
Start Setup Time
t HD:DAT
t SU:DAT
t SU:STA
0
100
0.6
0.9
μs
ns
μs
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Setup Time
SDA and SCL Capacitive
Loading
EEPROM Write Time
t R
t F
t SU:STO
C B
t W
(Note 9)
(Note 9)
(Note 9)
(Note 10)
20+
0.1C B
20+
0.1C B
0.6
20
300
300
400
30
ns
ns
μs
pF
ms
NONVOLATILE MEMORY CHARACTERISTICS
(V CC = +4.75V to +5.25V)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EEPROM Write Cycles
+85°C (Note 11)
30,000
Note 1: All voltages are referenced to ground unless otherwise noted. Currents into the IC are positive, out of the IC negative.
Note 2: During fault conditions, the AC-coupled feedback values are allowed to be below the absolute max rating of the LCM1 or
OVD1 pin for up to 1 second.
Note 3: Voltage with respect to V DCB .
Note 4: Lamp overdrive and analog dimming (based on reduction of lamp current) are disabled.
Note 5: This is the minimum pulse width guaranteed to generate an output burst, which will generate the DS3881’s minimum burst
duty cycle. This duty cycle may be greater than the duty cycle of the PSYNC input. Once the duty cycle of the PSYNC input
is greater than the DS3881’s minimum duty cycle, the output’s duty cycle will track the PSYNC’s duty cycle. Leaving
PSYNC low (0% duty cycle) disables the GA1 and GB1 outputs in DPWM receiver mode.
Note 6: This is the maximum lamp frequency duty cycle that will be generated at GA1 or GB1 outputs with spread-spectrum modu-
lation disabled.
Note 7: I 2 C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I 2 C standard-
mode timing.
Note 8: After this period, the first clock pulse can be generated.
Note 9: C B —total capacitance allowed on one bus line in picofarads.
Note 10: EEPROM write time applies to all the EEPROM memory. EEPROM write begins after a stop condition occurs.
Note 11: Guaranteed by design.
4
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