参数资料
型号: DS3882E+
厂商: Maxim Integrated
文件页数: 23/31页
文件大小: 0K
描述: IC CCFL CNTRLR DUAL 28TSSOP
标准包装: 50
类型: CCFL 控制器
频率: 40 ~ 100 kHz
电流 - 电源: 12mA
电源电压: 4.75 V ~ 5.25 V
工作温度: -40°C ~ 105°C
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 管件
Dual-Channel Automotive CCFL Controller
Table 7. Control Register 2 (CR2) [Shadowed-EEPROM, F5h]
BIT
R/W
DEFAULT
NAME
FUNCTION
User Memory Write Protect
0
R/W
0
UMWP
0 = Write access blocked.
1 = Write access permitted.
DPWM Oscillator Range Select. When using an external source for the dimming clock,
1
R/W
0
POSCR0
these bits must be set to match the external oscillator’s frequency. When using a
resistor to set the dimming frequency, these bits plus the external resistor control the
frequency.
POSCR1
POSCR0
DIMMING CLOCK (DPWM)
FREQUENCY RANGE (Hz)
k (k Ω ? kHz)
2
R/W
0
POSCR1
0
0
0
1
22.5 to 55.0
45 to 110
1
2
1
1
0
1
90 to 220
180 to 440
4
8
Lamp Sample Rate Select. Determines the feedback samp le rate of the LCM inputs.
3
R/W
1
LSR0
LSR1
LSR0
SELECTED LAMP SAMPLE
RATE
EXAMPLE SAMPLE RATE
IF LAMP FREQUENCY IS
50kHz
0
0
0
1
4 Lamp Frequency Cycles
8 Lamp Frequency Cycles
12,500Hz
6,250Hz
4
R/W
0
LSR1
1
0
16 Lamp Frequency Cycles
3,125Hz
1
1
32 Lamp Frequency Cycles
1,563Hz
5
6
0
0
RSVD
RSVD
Reserved. This bit should be set to zero.
Reserved. This bit should be set to zero.
Power-Down. Logically ORed with the PDN pin. Setting this bit high resets the controller,
7
R/W
0
PDNE
clears the fault logic, and places the part in power-down mode. 0 = Normal. All circuitry is
off, except I 2 C interface.
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