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参数资料
| 型号： | DS80C400-FNY |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 58/97页 |
| 文件大小： | 0K |
| 描述： | IC MCU 75MHZ 16MB HP 100-LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS |
| 产品变化通告： | Product Discontinuation 20/Feb/2012 |
| 标准包装： | 90 |
| 系列： | 80C |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 75MHz |
| 连通性： | 1 线，CAN，EBI/EMI，以太网，SIO，UART/USART |
| 外围设备： | 电源故障复位，WDT |
| 输入/输出数： | 64 |
| 程序存储器容量： | 64KB（64K x 8） |
| 程序存储器类型： | ROM |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.62 V ~ 3.6 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 包装： | 托盘 |
| 配用： | DS80C400-KIT#-ND - EVAL KIT FOR DS80C400 |
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DS80C400 Network Microcontroller
61 of 97
MII I/O Block
The MII I/O block supports all of the transmit and receive data transactions between the DS80C400 MAC and the
external PHY device as well as monitoring network status signals provided by the PHY.
The transmit interface is composed of TXCLK, TX_EN, and TXD[3:0]. The TXCLK input is the transmit clock
provided by the PHY. For 10Mbps operation, the transmit clock (TXCLK) should be run at 2.5MHz. For 100Mbps,
TXCLK should be run at 25MHz. The TXD[3:0] outputs provide the 4-bit (nibble) data bus for transmitting frame
data to the external PHY. Each transmission begins when the TX_EN output is driven active high, indicating to the
PHY that valid data is present on the TXD[3:0] bus.
The receive interface is composed of RXCLK, RX_DV, RX_ER, and RXD[3:0]. The RXCLK input is the receive
clock provided by the external PHY. This clock (RXCLK) should be run at 2.5MHz for 10Mbps operation and at
25MHz for 100Mbps operation. The RXD[3:0] inputs serve as the 4-bit (nibble) data bus for receiving frame data
from the external PHY. The reception begins when the external PHY drives the RX_DV input high, signaling that
valid data is present on the RXD[3:0] bus. During reception of a frame (RX_DV = 1), the RX_ER input indicates
whether the external PHY has detected an error in the current frame. The RX_ER input is ignored when not
receiving a frame (RX_DV = 0).
The MII also monitors two network status signals that are provided by the external PHY. The CRS (carrier sense)
input is used to assess when the physical media is idle. The COL (collision detect) input is required for half-duplex
operation to signal when a collision has occurred on the physical media.
Ethernet Frames
The basic purpose of the MII I/O block is to deliver and receive Ethernet frames to and from an external PHY,
which controls the physical carrier. The format of the IEEE 802.3 Ethernet frame is shown in Figure 6.
The preamble (7 Bytes) and start-of-frame delimiter (1 Byte) precede the Ethernet frame as a means of
synchronizing to the start of the frame. The first two fields of the Ethernet frame are the destination address and the
source address, each made up of 6 octets (bytes). The destination address field is the field examined by the
address check block to determine whether the applied address filter criteria is met or not. The two bytes following
the source address contain the Length or Type of frame. For Ethernet II (DIX) frames, these two bytes contain the
Type field and the protocol for that specific frame type is embedded in the Data field. For frames where Length is
specified in these two bytes, a header would typically follow in the Data field to convey type/protocol information for
the frame (i.e., 802.2 or SNAP). Since the maximum Data field length for an Ethernet frame is 1500 Bytes, and all
assigned frame types are greater than this value (1500d = 05DCh), one can easily distinguish whether the field
holds Type or Length, allowing both kinds of frames to co-exist on the network. A special case occurs when the
VLAN tag protocol ID (= 8100h) is encountered where the Length or Type is normally expected. The frame is then
considered to be VLAN tagged. The VLAN frame format is described later.
Figure 6. IEEE 802.3 Ethernet Frame
ETHERNET FRAME
PREAMBLE SFD
DESTINATION ADDRESS SOURCE ADDRESS
TYPE/LENGTH
DATA
CRC-32
(7)
(1)
(6)
(2)
(46-1500)
(4)
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相关代理商/技术参数 |
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| DS80C400-FNY+ | 功能描述:8位微控制器 -MCU Network MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| DS80C400-KIT | 功能描述:EVAL KIT FOR DS80C400 RoHS:否 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:- 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| DS80C400-KIT# | 功能描述:开发板和工具包 - 8051 RoHS:否 制造商:Silicon Labs 产品:Development Kits 工具用于评估:C8051F960, Si7005 核心: 接口类型:USB 工作电源电压: |
| DS80C410 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Network Microcontrollers with Ethernet and CAN |
| DS80C410_09 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Network Microcontrollers with Ethernet and CAN |
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