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| 型号： | DS87C550-QCL+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 20/49页 |
| 文件大小： | 0K |
| 描述： | IC MCU EPROM ADC/PWM HS 68-PLCC |
| 标准包装： | 18 |
| 系列： | 87C |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 33MHz |
| 连通性： | EBI/EMI，SIO，UART/USART |
| 外围设备： | 电源故障复位，PWM，WDT |
| 输入/输出数： | 55 |
| 程序存储器容量： | 8KB（8K x 8） |
| 程序存储器类型： | OTP |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 数据转换器： | A/D 6x10b |
| 振荡器型： | 外部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 68-LCC（J 形引线） |
| 包装： | 管件 |
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DS87C550 EPROM High-Speed Microcontroller with ADC and PWM
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interrupt. To enable the interrupt, the Timer 2 interrupt enable bit ET2 (EIE.7) must be set to a 1. The 8-
bit overflow interrupt or the 16-bit overflow interrupt is then individually enabled by setting TF2BS
(T2SEL.6) or TF2S (T2SEL.7). Since there is only one interrupt vector for both possible Timer 2
interrupts, the interrupt service routine must determine which event caused the interrupt by polling the
available flags. For both interrupt flags, software must clear them upon servicing the interrupt. There is
no automatic hardware clearing of these flags.
TIMER 2 CAPTURE FEATURE
One of the new features added to Timer 2 is the capture function. The output of Timer 2 is available to
four independent 16-bit capture register pairs (CPTH3:CPTL3, CPTH2:CPTL2, CPTH1:CPTL1, &
CPTH0:CPTL0). These registers are loaded with the 16-bit value contained in Timer 2 when transitions
occur on the corresponding input pin INT5/CT3, INT4/CT2, INT3/CT1 or INT2/CT0 (P1.3, P1.2, P1.1,
or P1.0) respectively. When the capture function is not being used, these input pins also serve as external
interrupt inputs. The Capture Trigger Control register (CTCON) can be programmed to make the capture
occur on a rising edge, a falling edge, or on either a rising or a falling edge on these input pins. The
functionality of the CTCON register is illustrated below. Note that the edge sensitivity established by the
setting of CTCON bits applies to both the capture function and the external interrupt function of these
input pins. This addition allows maximum flexibility in selecting interrupt polarity. Whether these input
pins are used as external interrupt inputs or as capture commands, the input will set the appropriate flag in
the External Interrupt Flag register (T2IR.3:0) and will create an interrupt if the associated enable in the
Extended Interrupt Enable (EIE.3:0) register is set.
CTCON REGISTER FUNCTIONALITY
CTCON.7
CT3
Capture register 3 triggered by a falling edge on INT5/CT3
CTCON.6
CT3
Capture register 3 triggered by a rising edge on INT5/CT3
CTCON.5
CT2
Capture register 2 triggered by a falling edge on INT4/CT2
CTCON.4
CT2
Capture register 2 triggered by a rising edge on INT4/CT2
CTCON.3
1
CT
Capture register 1 triggered by a falling edge on INT3/CT1
CTCON.2
CT1
Capture register 1 triggered by a rising edge on INT3/CT1
CTCON.1
CT0
Capture register 0 triggered by a falling edge on INT2/CT0
CTCON.0
CT0
Capture register 0 triggered by a rising edge on INT2/CT0
TIMER 2 COMPARE FEATURE
Another new feature added to Timer 2 capabilities is the compare function. Prior to enabling this
function, the associated compare register pair (CMPH0:CMPL0, CMPH1:CMPL1, CMPH2:CMPL2) is
loaded by software with a 16-bit number. Each time Timer 2 is incremented, the contents of these
registers are compared with the new value of the timer. When a match occurs, the corresponding interrupt
flag (T2IR.6:4) is set to a 1 on the next machine cycle and an interrupt will occur if the corresponding
enable bit is set in the Extended Interrupt Enable (EIE.6:4) register. When a match with CMPH0:CMPL0
occurs, port pins P4.0 through P4.5 are set to a 1 if the corresponding bits of the Set Enable register
(SETR) are at logic 1. If the match is with CMPH1:CMPL1, port pins P4.0 through P4.5 are reset to 0
when the corresponding bits in the reset/toggle enable register RSTR are at logic 1. A match with
CMPH2:CMPL2 toggles port pins P4.6 and 4.7 if the corresponding bits in the RSTR register are at logic
1. Note that for the toggle function it is not the port pin latch that is actually toggled. Instead, separate
flip-flops output the SFR bits TGFF1 and TGFF0 that actually determine the state of the respective port
pin. A 0 in a bit position in either the SETR or the RSTR register disables the corresponding port pin
function. The functionality of the SETR and RSTR registers is shown below.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS87C550-QCL+ | 功能描述:IC MCU EPROM ADC/PWM HS 68-PLCC RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:87C 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:260 系列:73S12xx 核心处理器:80515 芯体尺寸:8-位 速度:24MHz 连通性:I²C，智能卡，UART/USART，USB 外围设备:LED，POR，WDT 输入/输出数:9 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:2K x 8 电压 - 电源 (Vcc/Vdd):2.7 V ~ 5.5 V 数据转换器:- 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:68-VFQFN 裸露焊盘 包装:管件 |
| DS87C550-QCW | 制造商:Maxim Integrated Products 功能描述:DS87C550 WAIVERED FOR LS & MARKING - Rail/Tube |
| DS87C550-QNL | 功能描述:IC MCU EPROM ADC/PWM HS 68-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:87C 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:260 系列:73S12xx 核心处理器:80515 芯体尺寸:8-位 速度:24MHz 连通性:I²C，智能卡，UART/USART，USB 外围设备:LED，POR，WDT 输入/输出数:9 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:2K x 8 电压 - 电源 (Vcc/Vdd):2.7 V ~ 5.5 V 数据转换器:- 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:68-VFQFN 裸露焊盘 包装:管件 |
| DS88 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog IC |
| DS8800 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Dual Voltage Level Translator |
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