参数资料
型号: DS87C550-QCL+
厂商: Maxim Integrated Products
文件页数: 31/49页
文件大小: 0K
描述: IC MCU EPROM ADC/PWM HS 68-PLCC
标准包装: 18
系列: 87C
核心处理器: 8051
芯体尺寸: 8-位
速度: 33MHz
连通性: EBI/EMI,SIO,UART/USART
外围设备: 电源故障复位,PWM,WDT
输入/输出数: 55
程序存储器容量: 8KB(8K x 8)
程序存储器类型: OTP
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
数据转换器: A/D 6x10b
振荡器型: 外部
工作温度: 0°C ~ 70°C
封装/外壳: 68-LCC(J 形引线)
包装: 管件
DS87C550 EPROM High-Speed Microcontroller with ADC and PWM
37 of 49
AC ELECTRICAL CHARACTERISTICS
33MHz
VARIABLE CLOCK
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
Oscillator Freq. (Ext. Osc.)
(Ext. Crystal)
1/tCLCL
0
1
33
0
1
33
MHz
ALE Pulse Width
tLHLL
40
0.375 tMCS -5
ns
Port 0 Address Valid to ALE Low
tAVLL
9
0.125 tMCS -5
ns
Address Hold after ALE Low
tLLAX1
10
0.125 tMCS -5
ns
ALE Low to Valid Instruction In
tLLIV
60
0.625
tMCS -20
ns
ALE Low to PSEN Low
tLLPL
10
0.125 tMCS -5
ns
PSEN Pulse Width
tPLPH
55
0.5 tMCS -5
ns
PSEN Low to Valid Instruction In
tPLIV
41
0.5tMCS
-20
ns
Input Instruction Hold after PSEN
tPXIX
0
ns
Input Instruction Float after PSEN
tPXIZ
26
0.25tMCS -5
ns
Port 0 Address to Valid Instruction
In
tAVIV
77
0.75tMCS -
20
ns
Port 2 Address to Valid Instruction
In
tAVIV2
81
0.875
tMCS -25
ns
PSEN Low to Address Float
tPLAZ
0
ns
NOTES FOR AC ELECTRICAL CHARACTERISTICS
§ tMCS is a time period related to the machine cycle clock and the processor’s input clock frequency. Its value is
highlighted in the table “STRETCH VALUE TIMING” for all possible settings of the 4X/ 2X and CD1:0 bits.
The default condition is CD1 = 1 and CD0 = 0, where 4X/ 2X is disregarded.
§ All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
Electrical characterizations are not 100% tested but are guaranteed by design and characterization.
§ All signals characterized with load capacitance of 80 pF except Port 0, ALE, PSEN , RD and WR with 100
pF.
§ Interfacing to memory devices with float times (turn off times) over 25 ns may cause contention. This will not
damage the parts, but will cause an increase in operating current.
§ Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing will change in relation to
duty cycle variation.
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