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| 型号： | DS87C550-QCL+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 22/49页 |
| 文件大小： | 0K |
| 描述： | IC MCU EPROM ADC/PWM HS 68-PLCC |
| 标准包装： | 18 |
| 系列： | 87C |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 33MHz |
| 连通性： | EBI/EMI，SIO，UART/USART |
| 外围设备： | 电源故障复位，PWM，WDT |
| 输入/输出数： | 55 |
| 程序存储器容量： | 8KB（8K x 8） |
| 程序存储器类型： | OTP |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 数据转换器： | A/D 6x10b |
| 振荡器型： | 外部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 68-LCC（J 形引线） |
| 包装： | 管件 |
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DS87C550 EPROM High-Speed Microcontroller with ADC and PWM
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The watchdog timer uses the internal system clock as a time base so its timeout periods are very accurate.
From the table, it can be seen that for a 33MHz crystal frequency, the watchdog timer is capable of
producing timeout periods from 3.97 ms (217 * 1/33MHz) to over two seconds (2.034 = 226 * 1/33MHz)
with the default setting of CD1:0 (=10). This wide variation in timeout periods allows very flexible
system implementation.
In a typical initialization, the user selects one of the possible counter values to determine the timeout.
Once the counter chain has completed a full count, hardware will set the interrupt flag
(WDIF=WDCON.3). There is no hardware support for a watchdog interrupt, but this flag may be polled
to determine if the timeout period has been completed. Regardless of whether the software makes use of
this flag, there are then 512 clocks left until the reset flag (WTRF=WDCON.2) is set. Software can
enable (1) or disable (0) the reset using the Enable Watchdog Reset (EWT=WDCON.1) bit. Note that the
watchdog is a free running timer and does not require an enable.
POWER-FAIL RESET
The DS87C550 incorporates an internal precision band-gap voltage reference which, when coupled with
a comparator circuit, provides a full power-on and power-fail reset function. This circuit monitors the
processor’s incoming power supply voltage (VCC) and holds the processor in reset while VCC is out of
tolerance. Once VCC has risen above VRST, the DS87C550 will restart the oscillator for the external crystal
and count 65,536 clock cycles before program execution begins at location 0000h. This power supply
monitor will also invoke the reset state when VCC drops below the threshold condition. This reset
condition will remain while power is below the minimum voltage level. When power exceeds the reset
threshold, a full power-on reset will be performed. In this way, this internal voltage monitoring circuitry
handles both power-up and power down conditions without the need for additional external components.
The processor exits the reset condition automatically once VCC meets VRST. This helps the system
maintain reliable operation by only permitting processor operation when its supply voltage is in a known
good state. Software can determine that a Power-On Reset has occurred by checking the Power-On Reset
flag (POR=WDCON.6). Software should clear the POR bit after reading it.
The Reset pin of the DS87C550 is both an input and an output. When the processor is being held in reset
by the power-fail detection circuitry, the reset pin will be actively pulled high by the processor, and can
therefore be used as an input to other external devices.
POWER-FAIL INTERRUPT
The band-gap voltage reference that sets a precise reset threshold also generates an optional early warning
Power-fail Interrupt (PFI). When enabled by software, the processor will vector to ROM address 0033h if
VCC drops below VPFW. PFI has the highest priority. The PFI enable is in the Watchdog Control SFR
(EPFI=WDCON.5). Setting this bit to a logic 1 will enable the PFI. Application software can also read
the PFI flag at WDCON.4. A PFI condition sets this bit to a 1. The flag is independent of the interrupt
enable and software must manually clear it.
INTERRUPTS
The DS87C550 provides 16 interrupt sources with three priority levels. The Power-fail Interrupt (PFI) has
the highest priority. All interrupts, with the exception of the Power-fail Interrupt, are controlled by a
series combination of individual enable bits and a global interrupt enable EA (IE.7). Setting EA to a 1
allows individual interrupts to be enabled. Clearing EA disables all interrupts regardless of their
individual enable settings.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS87C550-QCL+ | 功能描述:IC MCU EPROM ADC/PWM HS 68-PLCC RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:87C 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:260 系列:73S12xx 核心处理器:80515 芯体尺寸:8-位 速度:24MHz 连通性:I²C，智能卡，UART/USART，USB 外围设备:LED，POR，WDT 输入/输出数:9 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:2K x 8 电压 - 电源 (Vcc/Vdd):2.7 V ~ 5.5 V 数据转换器:- 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:68-VFQFN 裸露焊盘 包装:管件 |
| DS87C550-QCW | 制造商:Maxim Integrated Products 功能描述:DS87C550 WAIVERED FOR LS & MARKING - Rail/Tube |
| DS87C550-QNL | 功能描述:IC MCU EPROM ADC/PWM HS 68-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:87C 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:260 系列:73S12xx 核心处理器:80515 芯体尺寸:8-位 速度:24MHz 连通性:I²C，智能卡，UART/USART，USB 外围设备:LED，POR，WDT 输入/输出数:9 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:2K x 8 电压 - 电源 (Vcc/Vdd):2.7 V ~ 5.5 V 数据转换器:- 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:68-VFQFN 裸露焊盘 包装:管件 |
| DS88 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog IC |
| DS8800 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Dual Voltage Level Translator |
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