参数资料
型号: DS89C430-QNG+
厂商: Maxim Integrated Products
文件页数: 35/46页
文件大小: 0K
描述: IC MCU FLASH 16KB 25MHZ 44-PLCC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 26
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 25MHz
连通性: EBI/EMI,SIO,UART/USART
外围设备: 电源故障复位,WDT
输入/输出数: 32
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 管件
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers
40 of 46
Watchdog Timer
The watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. When the clock
divider is set to 10b, the interrupt timeout has a default divide ratio of 217 of the crystal oscillator clock, with the
watchdog reset set to time out 512 system clock cycles later. This results in a 33MHz crystal oscillator producing
an interrupt timeout every 3.9718ms, followed 15.5s later by a watchdog reset. The watchdog timer is reset to the
default divide ratio following any reset. Using the WD0 and WD1 bits in the clock control (CKCON.6 and 7) register,
other divide ratios can be selected for longer watchdog interrupt periods. Table 13 summarizes the watchdog bits
settings and the timeout values.
Note: All watchdog timer reset timeouts follow the programmed interrupt timeouts
by 512 system clock cycles, which equates to varying numbers of oscillator cycles depending on the clock divide
(CD1:0) and crystal multiplier settings.
Table 13. Watchdog Timeout Value (In Number of Oscillator Clocks)
WATCHDOG INTERRUPT TIMEOUT
WATCHDOG RESET TIMEOUT
4X/2X CD1:0
WD1:0 = 00 WD1:0 = 01 WD1:0 = 10 WD1:0 = 11
WD1:0 = 00
WD1:0 = 01
WD1:0 = 10
WD1:0 = 11
1
00
215
218
221
224
215 + 128
218 + 128
221 + 128
224 + 128
0
00
216
219
222
225
216 + 256
219 + 256
222 + 256
225 + 256
x
01
217
220
223
226
217 + 512
220 + 512
223 + 512
226 + 512
x
10
217
220
223
226
217 + 512
220 + 512
223 + 512
226 + 512
x
11
227
230
233
236
227 + 524,288
230 + 524,288
233 + 524,288
236 + 524,288
A watchdog control (WDCON) SFR is used for programming the functions. EWT (WDCON.1) is the enable for the
watchdog timer-reset function and RWT (WDCON.0) is the bit used to restart the watchdog timer. Setting the RWT
bit restarts the timer for another full interval. If the watchdog timer-reset function is masked by the EWT bit and no
resets are issued to the timer through the RWT bit, the watchdog timer generates interrupt timeouts at a rate
determined by the programmed divide ratio. WDIF (WDCON.3) is the interrupt flag set at timer termination and
WTRF (WDCON.2) is the reset flag set following a watchdog reset timeout. Setting the EWDI bit (EIE.4) enables
the watchdog interrupt. The watchdog timer reset and interrupt timeouts are measured by counting system clock
cycles.
An independent watchdog timer functions as the crystal startup counter to count 65,536 crystal clock cycles before
allowing the crystal oscillator to function as the system clock. This warmup time is verified by the watchdog timer
following each power-up as well as each time the crystal is restarted following a stop mode. The watchdog is also
used to establish a startup time whenever the CTM in the PMR register is set to enable the crystal multiplier
(4X
/2X).
One of the watchdog timer applications is for the watchdog to wake up the system from idle mode. The watchdog
interrupt can be programmed to allow a system to wake up periodically to sample the external world.
Internal System Reset
A software reset can be initiated by writing a system reset command to the flash control SFR. The reset state is
maintained for approximately 90 external clock cycles. During this time, the RST pin is driven to a logic high. Once
the reset is removed, the RST pin is driven low, and operation begins from address 0000h.
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