参数资料
型号: DSP56F803BU80
厂商: Freescale Semiconductor
文件页数: 24/52页
文件大小: 0K
描述: IC DSP 80MHZ 64KB FLASH 100LQFP
标准包装: 90
系列: 56F8xx
核心处理器: 56800
芯体尺寸: 16-位
速度: 80MHz
连通性: CAN,EBI/EMI,SCI,SPI
外围设备: POR,PWM,WDT
输入/输出数: 16
程序存储器容量: 71KB(35.5K x 16)
程序存储器类型: 闪存
RAM 容量: 2.5K x 16
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 8x12b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
包装: 托盘
56F803 Technical Data, Rev. 16
30
Freescale Semiconductor
3.5.4
Phase Locked Loop Timing
3.6 External Bus Asynchronous Timing
Table 3-9 PLL Timing
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL1
1.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2.
ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the
User Manual. ZCLK = fop
3.
This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
fosc
48
10
MHz
PLL output frequency 2
fout/2
40
110
MHz
PLL stabilization time 3 0o to +85oC
tplls
—1
10
ms
PLL stabilization time3 -40o to 0oC
tplls
100
200
ms
Table 3-10 External Bus Asynchronous Timing1, 2
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL 50pF, fop = 80MHz
Characteristic
Symbol
Min
Max
Unit
Address Valid to WR Asserted
tAWR
6.5
ns
WR Width Asserted
Wait states = 0
Wait states > 0
tWR
7.5
(T*WS) + 7.5
ns
WR Asserted to D0–D15 Out Valid
tWRD
—4.2
ns
Data Out Hold Time from WR Deasserted
tDOH
4.8
ns
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
tDOS
2.2
(T*WS) + 6.4
ns
RD Deasserted to Address Not Valid
tRDA
0—
ns
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
tARDD
18.7
(T*WS) + 18.7
ns
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