参数资料
型号: DSP56F803BU80
厂商: Freescale Semiconductor
文件页数: 26/52页
文件大小: 0K
描述: IC DSP 80MHZ 64KB FLASH 100LQFP
标准包装: 90
系列: 56F8xx
核心处理器: 56800
芯体尺寸: 16-位
速度: 80MHz
连通性: CAN,EBI/EMI,SCI,SPI
外围设备: POR,PWM,WDT
输入/输出数: 16
程序存储器容量: 71KB(35.5K x 16)
程序存储器类型: 闪存
RAM 容量: 2.5K x 16
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 8x12b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
包装: 托盘
56F803 Technical Data, Rev. 16
32
Freescale Semiconductor
Figure 3-11 External Bus Asynchronous Timing
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1.
Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2.
Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing 1, 5
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL 50pF
Characteristic
Symbol
Min
Max
Unit
See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ
—21
ns
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
tRA
275,000T
128T
ns
RESET De-assertion to First External Address Output
tRDA
33T
34T
ns
A0–A15,
PS, DS
(See Note)
WR
D0–D15
RD
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Data In
Data Out
tAWR
tARDA
tARDD
tRDA
tRD
tRDRD
tRDWR
tWRWR
tWR
tDOS
tWRD
tWRRD
tAD
tDOH
tDRD
tRDD
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