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| 型号： | DSP56F805FV80E |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 28/56页 |
| 文件大小： | 0K |
| 描述： | IC DSP 80MHZ 64KB FLASH 144LQFP |
| 标准包装： | 60 |
| 系列： | 56F8xx |
| 核心处理器： | 56800 |
| 芯体尺寸： | 16-位 |
| 速度： | 80MHz |
| 连通性： | CAN，EBI/EMI，SCI，SPI |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 32 |
| 程序存储器容量： | 71KB（35.5K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 2.5K x 16 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 8x12b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 144-LQFP |
| 包装： | 托盘 |
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56F805 Technical Data, Rev. 16
34
Freescale Semiconductor
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 6
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
1.
In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
Characteristic
Symbol
Min
Max
Unit
See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ
—21
ns
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
2.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
After power-on reset
When recovering from Stop state
tRA
275,000T
128T
—
ns
RESET Deassertion to First External Address Output
tRDA
33T
34T
ns
Edge-sensitive Interrupt Request Width
tIRW
1.5T
—
ns
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
tIDM
15T
—
ns
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
16T
—
ns
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State3
3.
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
tIRI
13T
—
ns
IRQA Width Assertion to Recover from Stop State4
4.
The interrupt instruction fetch is visible on the pins only in Mode 3.
tIW
2T
—
ns
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIF
—
275,000T
12T
ns
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
—
275,000T
12T
ns
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tII
—
275,000T
12T
ns
RSTO pulse width5
normal operation
internal reset mode
5.
ET = External Clock period, For an external crystal frequency of 8MHz, ET=125ns.
6.
Parameters listed are guaranteed by design.
tRSTO
63ET
2,097,151ET
ns
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相关代理商/技术参数 |
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|---|---|
| DSP56F805FV80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
| DSP56F805FV80E | 制造商:Freescale Semiconductor 功能描述:DSP LQFP144 3.6V |
| DSP56F805PB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:56F805 16-Bit Hybrid Controller Product Brief |
| DSP56F807 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:56F807 16-bit Hybrid Processor |
| DSP56F807EVM | 功能描述:开发板和工具包 - 其他处理器 Evaluation Kit For DSP56F807 RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
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