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参数资料
型号： DSPB56371AF180
厂商： Freescale Semiconductor
文件页数： 67/68页
文件大小： 0K
描述： IC DSP 24BIT 180MHZ 80-LQFP
标准包装： 90
系列： DSP56K/Symphony
类型： 音频处理器
接口： 主机接口，I²C，SAI，SPI
时钟速率： 180MHz
非易失内存： ROM（384 kB）
芯片上RAM： 264kB
电压 - 输入/输出： 3.30V
电压 - 核心： 1.25V
工作温度： -40°C ~ 115°C
安装类型： 表面贴装
封装/外壳： 80-LQFP
供应商设备封装： 80-LQFP（14x14）
包装： 托盘
DSP56371 Data Sheet, Rev. 4.1
DSP56371 Overview
Freescale Semiconductor
8
Triggering from interrupt lines and all peripherals
2.4.6
PLL-based Clock Oscillator
The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which performs
clock input division, frequency multiplication, skew elimination and the clock generator (CLKGEN),
which performs low-power division and clock pulse generation. PLL-based clocking:
Allows change of low-power divide factor (DF) without loss of lock
Provides output clock with skew elimination
Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL
feedback multiplier (2 or 4), output divide factor (1, 2 or 4), and a power-saving clock divider
(2i: i = 0 to 7) to reduce clock noise
The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock
input. This feature offers two immediate benefits:
A lower frequency clock input reduces the overall electromagnetic interference generated by a
system.
The ability to oscillate at different frequencies reduces costs by eliminating the need to add
additional oscillators to a system.
NOTE
The PLL will momentarily overshoot the target frequency when the PLL is first enabled or
when the VCO frequency is modified. It is important that when modifying the PLL
frequency or enabling the PLL that the two-step procedure defined in Section 3, DSP56371
Overview be followed.
2.4.7
On-Chip Memory
The memory space of the DSP56300 core is partitioned into program memory space, X data memory space
and Y data memory space. The data memory space is divided into X and Y data memory in order to work
with the two Address ALUs and to feed two operands simultaneously to the Data ALU. Memory space
includes internal RAM and ROM and can not be expanded off-chip.
There is an instruction patch module. The patch module is used to patch program ROM. The memory
switch mode is used to increase the size of program RAM as needed (switch from X data RAM and/or Y
data RAM).
There are on-chip ROMs for program and bootstrap memory (64K x 24-bit), X ROM (32K x 24-bit) and
Y ROM (32K x 24-bit).
More information on the internal memory is provided in the DSP56371 User’s Manual, Memory section.
2.4.8
Off-Chip Memory Expansion
Memory cannot be expanded off-chip. There is no external memory bus.
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DSPB56371AF180 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor (DSP) IC
DSPB56374AE 功能描述:数字信号处理器和控制器 - DSP, DSC PB-FREE 52 LQFP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSPB56374AEB 制造商:Freescale Semiconductor 功能描述:52 LQFP PB-FREE W/ BI - Bulk
DSPB56374AEC 功能描述:数字信号处理器和控制器 - DSP, DSC 52 LQFP AUTOMOTIVE RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSPB56374AF 功能描述:数字信号处理器和控制器 - DSP, DSC PB-FREE 80 LQFP 14X14MM RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
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