参数资料
型号: DSPB56724AG
厂商: Freescale Semiconductor
文件页数: 19/48页
文件大小: 0K
描述: DSP 24BIT AUD 250MHZ 144-LQFP
标准包装: 60
系列: DSP56K/Symphony
类型: 音频处理器
接口: 主机接口,I²C,SAI,SPI
时钟速率: 250MHz
非易失内存: 外部
芯片上RAM: 112kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 144-LQFP
供应商设备封装: 144-LQFP(20x20)
包装: 托盘
Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
Freescale Semiconductor
26
92
FST input (wl) to data out enable from high impedance
21.0
ns
93
FST input (wl) to transmitter #0 drive enable assertion
14.0
ns
94
Flag output valid after SCKT rising edge
14.0
9.0
x ck
i ck
ns
95
HCKR/HCKT clock cycle
2
× TC
10
ns
96
HCKT input rising edge to SCKT output
18.0
ns
97
HCKR input rising edge to SCKR output
18.0
ns
Note:
1. 0.95 V < VVDD_CORE < 1.05 V and Tj < 100° C, CL = 50 pF
2. i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that SCKT and SCKR are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that SCKT and SCKR are the same clock)
3. bl = bit length
wl = word length
wr = word length relative
4. SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
5. For the internal clock, the external clock cycle is defined by Tc and the ESAI control register.
6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one
before last bit clock of the first word in frame.
7. Periodically sampled and not 100% tested.
8. ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI.
Table 11. Enhanced Serial Audio Interface Timing (Continued)
No.
Characteristics1, 2, 3
Symbol Expression3
Min
Max
Condition4 Unit
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