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| 型号： | DSPB56724AG |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 4/48页 |
| 文件大小： | 0K |
| 描述： | DSP 24BIT AUD 250MHZ 144-LQFP |
| 标准包装： | 60 |
| 系列： | DSP56K/Symphony |
| 类型： | 音频处理器 |
| 接口： | 主机接口，I²C，SAI，SPI |
| 时钟速率： | 250MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 112kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
Freescale Semiconductor
12
19
Duration of level sensitive IRQA assertion to ensure interrupt
service (when exiting Stop)1, 2, 3
PLL is active during Stop and Stop delay is enabled (OMR Bit
6 = 0)
(128 Kbytes
× TC)
655
—
μs
PLL is active during Stop and Stop delay is not enabled (OMR
Bit 6 = 1)
25
× TC
125
—
ns
PLL is not active during Stop and Stop delay is enabled (OMR
Bit 6 = 0)
(128KxTC) + PLLLOCK
855
—
μs
PLL is not active during Stop and Stop delay is not enabled
(OMR Bit 6 = 1)
(25
× TC) + PLLLOCK
200
—
μs
20
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
general-purpose transfer output valid caused by first interrupt
instruction execution1
10
× TC + 3.8
—
53.8
ns
21
Interrupt Requests Rate1
ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_1
12
× TC
—
60.0
ns
DMA
8
× TC
—
40.0
ns
IRQ, NMI (edge trigger)
8
× TC
—
40.0
ns
IRQ (level trigger)
12
× TC
—
60.0
ns
22
DMA Requests Rate
Data read from ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1
6
× TC
—
30.0
ns
Data write to ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1
7
× TC
—
35.0
ns
Timer, Timer_1
2
× TC
—
10.0
ns
IRQ, NMI (edge trigger)
3
× TC
—
15.0
ns
Note:
1. When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply
to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using
fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
2. For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined
by the OMR Bit 6 settings.
For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shut down during Stop. Recovering from Stop requires the PLL
to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200 us.
3. Periodically sampled and not 100% tested.
4. RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and
valid. When VDD is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the
device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should
minimize this state to the shortest possible duration.
Table 7. Reset, Stop, Mode Select, and Interrupt Timing (Continued)
No.
Characteristics
Expression
Min
Max
Unit
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DSPB56724CAG | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Symphony? DSP56724/DSP56725 Multi-Core Audio Processors |
| DSPB56725AF | 功能描述:数字信号处理器和控制器 - DSP, DSC Multi-Core Audio Processor 80-Pin RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSPB56725CAF | 功能描述:数字信号处理器和控制器 - DSP, DSC PB FREE DSPB56724 AP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSPB720DB1E | 功能描述:子卡和OEM板 B VERSION 720 DAUGHTER C RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| DSPB721DB1E | 功能描述:子卡和OEM板 B VERSION 721 DAUGHTER C RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
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