参数资料
型号: DSPIC33FJ12MC201T-I/SS
厂商: Microchip Technology
文件页数: 67/155页
文件大小: 0K
描述: IC DSPIC MCU/DSP 12K 20SSOP
产品培训模块: Asynchronous Stimulus
标准包装: 1,600
系列: dsPIC™ 33F
核心处理器: dsPIC
芯体尺寸: 16-位
速度: 40 MIP
连通性: I²C,IrDA,SPI,UART/USART
外围设备: 高级欠压探测/复位,电机控制 PWM,QEI,POR,PWM,WDT
输入/输出数: 15
程序存储器容量: 12KB(12K x 8)
程序存储器类型: 闪存
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 20-SSOP(0.209",5.30mm 宽)
包装: 带卷 (TR)
配用: DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名称: DSPIC33FJ12MC201T-I/SSTR
2010 Microchip Technology Inc.
DS41303G-page 293
PIC18F2XK20/4XK20
22.0
HIGH/LOW-VOLTAGE
DETECT (HLVD)
PIC18F2XK20/4XK20 devices have a High/Low-Voltage
Detect module (HLVD). This is a programmable circuit
that allows the user to specify both a device voltage trip
point and the direction of change from that point. If the
device experiences an excursion past the trip point in
that direction, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the inter-
rupt vector address and the software can then respond
to the interrupt.
The
High/Low-Voltage
Detect
Control
register
(Register 22-1) completely controls the operation of the
HLVD module. This allows the circuitry to be “turned
off” by the user under software control, which
minimizes the current consumption for the device.
The block diagram for the HLVD module is shown in
The module is enabled by setting the HLVDEN bit.
Each time that the HLVD module is enabled, the cir-
cuitry requires some time to stabilize. The IRVST bit is
a read-only bit and is used to indicate when the circuit
is stable. The module can only generate an interrupt
after the circuit is stable and IRVST is set.
The VDIRMAG bit determines the overall operation of
the module. When VDIRMAG is cleared, the module
monitors for drops in VDD below a predetermined set
point. When the bit is set, the module monitors for rises
in VDD above the set point.
REGISTER 22-1:
HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
R/W-0
U-0
R-0
R/W-0
R/W-1
R/W-0
R/W-1
VDIRMAG
IRVST
HLVDEN
HLVDL3(1)
HLVDL2(1)
HLVDL1(1)
HLVDL0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented
C = Clearable only bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
VDIRMAG: Voltage Direction Magnitude Select bit
1
= Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>)
0
= Event occurs when voltage equals or falls below trip point (HLVDL<3:0>)
bit 6
Unimplemented: Read as ‘0’
bit 5
IRVST: Internal Reference Voltage Stable Flag bit
1
= Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range
0
= Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage
range and the HLVD interrupt should not be enabled
bit 4
HLVDEN: High/Low-Voltage Detect Power Enable bit
1
= HLVD enabled
0
= HLVD disabled
bit 3-0
HLVDL<3:0>: Voltage Detection Limit bits(1)
1111
= External analog input is used (input comes from the HLVDIN pin)
1110
= Maximum setting
.
0000
= Minimum setting
Note 1:
See Table 26-4 for specifications.
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