参数资料
型号: DSPIC33FJ32GP202-I/SS
厂商: Microchip Technology
文件页数: 141/176页
文件大小: 0K
描述: IC DSPIC MCU/DSP 32K 28SSOP
标准包装: 47
系列: dsPIC™ 33F
核心处理器: dsPIC
芯体尺寸: 16-位
速度: 40 MIP
连通性: I²C,IrDA,LIN,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 21
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 10x10b/12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
包装: 管件
2007-2011 Microchip Technology Inc.
DS70290J-page 67
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
6.4
Power-on Reset (POR)
A Power-on Reset (POR) circuit ensures the device is
reset from power-on. The POR circuit is active until
VDD crosses the VPOR threshold and the delay TPOR
has elapsed. The delay TPOR ensures the internal
device bias circuits become stable.
The device supply voltage characteristics must meet
the
specified
starting
voltage
and
rise
rate
requirements to generate the POR. Refer to
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
6.4.1
Brown-out Reset (BOR) and
Power-up timer (PWRT)
The on-chip regulator has a Brown-out Reset (BOR)
circuit that resets the device when the VDD is too low
(VDD < VBOR) for proper device operation. The BOR
circuit keeps the device in Reset until VDD crosses
VBOR threshold and the delay TBOR has elapsed. The
delay TBOR ensures the voltage regulator output
becomes stable.
The BOR status bit in the Reset Control register
(RCON<1>) is set to indicate the Brown-out Reset.
The device will not run at full speed after a BOR as the
VDD should rise to acceptable levels for full-speed
operation. The PWRT provides power-up time delay
(TPWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
The power-up timer delay (TPWRT) is programmed by
the Power-on Reset Timer Value Select bits
(FPWRT<2:0>) in the POR Configuration register
(FPOR<2:0>), which provide eight settings (from 0 ms
for further details.
Figure 6-3 shows the typical brown-out scenarios. The
reset delay (TBOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point
TABLE 6-2:
OSCILLATOR PARAMETERS
Symbol
Parameter
Value
VPOR
POR threshold
1.8V nominal
TPOR
POR extension time
30
μs maximum
VBOR
BOR threshold
2.5V nominal
TBOR
BOR extension time
100
μs maximum
TPWRT
Programmable power-up time delay
0-128 ms nominal
TFSCM
Fail-Safe Clock Monitor Delay
900
μs maximum
Note:
When the device exits the Reset
condition (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges, otherwise
the device may not function correctly.
The user application must ensure that
the delay between the time power is
first applied, and the time SYSRST
becomes inactive, is long enough to get
all
operating
parameters
within
specification.
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