参数资料
型号: DSPIC33FJ32GP202-I/SS
厂商: Microchip Technology
文件页数: 143/176页
文件大小: 0K
描述: IC DSPIC MCU/DSP 32K 28SSOP
标准包装: 47
系列: dsPIC™ 33F
核心处理器: dsPIC
芯体尺寸: 16-位
速度: 40 MIP
连通性: I²C,IrDA,LIN,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 21
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 10x10b/12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
包装: 管件
2007-2011 Microchip Technology Inc.
DS70290J-page 69
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
6.9
Configuration Mismatch Reset
To maintain the integrity of the Peripheral Pin Select
control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occur (such as cell
disturbances caused by ESD or other external events),
a Configuration Mismatch Reset occurs.
The Configuration Mismatch Flag bit (CM) in the
Reset Control register (RCON<9>) is set to indicate
the
Configuration
Mismatch
Reset.
Refer
to
Section 10.0 “I/O Ports” for more information on the
Configuration Mismatch Reset.
6.10
Illegal Condition Device Reset
An illegal condition device Reset occurs due to the
following sources:
Illegal Opcode Reset
Uninitialized W Register Reset
Security Reset
The Illegal Opcode or Uninitialized W Access Reset
Flag bit (IOPUWR) in the Reset Control register
(RCON<14>) is set to indicate the illegal condition
device Reset.
6.10.1
ILLEGAL OPCODE RESET
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
The illegal opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the illegal opcode Reset, use only the lower 16 bits of
each program memory section to store the data values.
The upper 8 bits should be programmed with 3Fh,
which is an illegal opcode value.
6.10.2
UNINITIALIZED W REGISTER
RESET
Any attempts to use the uninitialized W register as an
address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
resets and is considered uninitialized until written to.
6.10.3
SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
branch instruction.
The VFC occurs when the Program Counter is
reloaded with an Interrupt or Trap vector.
CodeGuard Security” for more information on
Security Reset.
6.11
Using the RCON Status Bits
The user application can read the Reset Control
register (RCON) after any device Reset to determine
the cause of the reset.
Table 6-3 provides a summary of the reset flag bit
operation.
TABLE 6-3:
RESET FLAG BIT OPERATION
Note:
The
Configuration
Mismatch
Reset
feature and associated Reset flag are not
available on all devices.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
Flag Bit
Set by:
Cleared by:
TRAPR (RCON<15>)
Trap conflict event
POR,BOR
IOPWR (RCON<14>)
Illegal opcode or uninitialized
W register access or Security Reset
POR,BOR
CM (RCON<9>)
Configuration Mismatch
POR,BOR
EXTR (RCON<7>)
MCLR Reset
POR
SWR (RCON<6>)
RESET instruction
POR,BOR
WDTO (RCON<4>)
WDT time-out
PWRSAV instruction,
CLRWDT instruction, POR,BOR
SLEEP (RCON<3>)
PWRSAV #SLEEP instruction
POR,BOR
IDLE (RCON<2>)
PWRSAV #IDLE instruction
POR,BOR
BOR (RCON<1>)
POR, BOR
POR (RCON<0>)
POR
Note: All Reset flag bits can be set or cleared by user software.
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