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参数资料
| 型号： | EDI8L21665V |
| 英文描述： | 2x64Kx16 SRAM(2x64Kx16静态RAM) |
| 中文描述： | 2x64Kx16的SRAM（静态RAM的2x64Kx16） |
| 文件页数： | 3/5页 |
| 文件大小： | 138K |
| 代理商： | EDI8L21665V |
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI8L21665V
AC TEST CIRCUIT
AC TEST CONDITIONS
50
Vt = 1.5V
Output
Z0 = 50
Z0 = 50
Parameter
I/O
Unit
Input Pulse Levels
VSS to 3.0
V
Input Rise and Fall Times (max)
1.5
ns
Input and Output Timing Levels
1.5
V
Output Load
See figure, at left
AC Output Load Equivalent
1.25V
AC ELECTRICAL CHARACTERISTICS
Symbol
10ns
12ns
15ns
Read Cycle
Min
Max
Min
Max
Min
Max
Units
Read Cycle Time
tAVAV
10
12
15
ns
Address Access Time
tAVQV
10
12
15
ns
Chip Enable Access
tELQV
10
12
15
ns
Output Hold from Address Change
tAVQX
34
4
ns
Chip Enable to Output in Low-Z
tELQX
34
4
ns
Chip Disable to Output in High-Z
tEHQZ
56
7
ns
Output Enable access time
tGLQV
56
7
ns
Output Enable to Output in Low-Z
tGLQX
00
0
ns
Output Disable to Output in High-Z
tGHQZ
56
7
ns
Write Cycle
Write Cycle Time
tAVAV
10
12
15
ns
Chip Enable to End of Write
tELWH
88
9
ns
Address valid to End of Write, with G HIGH
tAVGHWH
88
9
ns
Address Setup Time
tAVWL
00
0
ns
Address Hold from End of Write
tAVWH
88
10
ns
Write Pulse Width
tWLWH
10
11
ns
Write Pulse Width, with G HIGH
tWLGHWH
88
9
ns
Data Setup Time
tDVWH
66
7
ns
Data Hold Time
tWHDX
00
0
ns
Write Disable to Output in Low-Z
tWHQX
34
5
ns
Write Enable to Output in High-Z
tWLQZ
56
7
ns
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