参数资料
型号: EFM32-TG-STK3300
厂商: Energy Micro
文件页数: 35/136页
文件大小: 0K
描述: KIT STARTER EFM32 GECKO
特色产品: EFM32 Tiny Gecko
标准包装: 1
系列: EFM®32
类型: MCU
适用于相关产品: EFM32-TGXXX
所含物品: 板,线缆,CD 和文档
其它名称: 914-1018
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
13
www.energymicro.com
Table 2.10. CONTROL register bit assignments
Bits
Name
Function
[31:2]
-
Reserved
[1]
Active stack pointer
Defines the current stack:
0 = MSP is the current stack pointer
1 = PSP is the current stack pointer.
In Handler mode this bit reads as zero and ignores writes.
[0]
Thread mode privilege level
Defines the Thread mode privilege level:
0 = privileged1 = unprivileged.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer
bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms update
the CONTROL register.
In an OS environment, it is recommended that threads running in Thread mode use the process stack
and the kernel and exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP,
use the MSR instruction to set the Active stack pointer bit to 1, see Section 3.10.7 (p. 83) .
Note
When changing the stack pointer, software must use an ISB instruction immediately after
the MSR instruction. This ensures that instructions after the ISB execute using the new stack
2.1.4 Exceptions and interrupts
The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested
Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the
normal flow of software control. The processor uses handler mode to handle all exceptions except for
reset. See Section 2.3.7.1 (p. 27) and Section 2.3.7.2 (p. 27) for more information.
The NVIC registers control interrupt handling. See Section 4.2 (p. 88) for more information.
2.1.5 Data types
The processor:
supports the following data types:
32-bit words
16-bit halfwords
8-bit bytes
supports 64-bit data transfer instructions.
manages all data memory accesses as little-endian. See Section 2.2.1 (p. 15) for more information.
2.1.6 The Cortex Microcontroller Software Interface Standard
For a Cortex-M3 microcontroller system, the Cortex Microcontroller Software Interface Standard
(CMSIS) defines:
a common way to:
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