- 您现在的位置：买卖IC网 > PDF目录17166 > EFM32-TG-STK3300 (Energy Micro)KIT STARTER EFM32 GECKO PDF资料下载
参数资料
| 型号： | EFM32-TG-STK3300 |
| 厂商： | Energy Micro |
| 文件页数： | 46/136页 |
| 文件大小： | 0K |
| 描述： | KIT STARTER EFM32 GECKO |
| 特色产品： | EFM32 Tiny Gecko |
| 标准包装： | 1 |
| 系列： | EFM®32 |
| 类型： | MCU |
| 适用于相关产品： | EFM32-TGXXX |
| 所含物品： | 板，线缆，CD 和文档 |
| 其它名称： | 914-1018 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页当前第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
17
www.energymicro.com
Address
range
Memory region
Memory
type
XN
Description
0x60000000
-
0x9FFFFFFF
External RAM
Normal
1
-
Executable region for data.
0xA0000000
-
0xDFFFFFFF
External device
Device
1
XN
1
External Device memory
0xE0000000
-
0xE00FFFFF
Private
Peripheral Bus
Strongly-
ordered
1
XN
1
This region includes the NVIC, System timer, and system control
block.
0xE0100000
-
0xFFFFFFFF
Reserved
Device
1
XN
1
Reserved
1See Section 2.2.1 (p. 15) for more information.
The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends that
programs always use the Code region. This is because the processor has separate buses that enable
instruction fetches and data accesses to occur simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see Section 4.5 (p. 113) .
2.2.4 Software ordering of memory accesses
The order of instructions in the program flow does not always guarantee the order of the corresponding
memory transactions. This is because:
the processor can reorder some memory accesses to improve efficiency, providing this does not affect
the behavior of the instruction sequence.
the processor has multiple bus interfaces
memory or devices in the memory map have different wait states
some memory accesses are buffered or speculative.
Section 2.2.2 (p. 16) describes the cases where the memory system guarantees the order of memory
accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier
instructions to force that ordering. The processor provides the following memory barrier instructions:
DMB
The
Data
Memory
Barrier
(DMB)
instruction
ensures
that
outstanding memory transactions complete before subsequent
memory transactions. See Section 3.10.3 (p. 81) .
DSB
The Data Synchronization Barrier (DSB) instruction ensures that
outstanding memory transactions complete before subsequent
instructions execute. See Section 3.10.4 (p. 82) .
ISB
The Instruction Synchronization Barrier (ISB) ensures that the effect
of all completed memory transactions is recognizable by subsequent
instructions. See Section 3.10.5 (p. 82) .
Use memory barrier instructions in, for example:
MPU programming:
Use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of context
switching.
Use an ISB instruction to ensure the new MPU setting takes effect immediately after programming
the MPU region or regions, if the MPU configuration code was accessed using a branch or call.
If the MPU configuration code is entered using exception mechanisms, then an ISB instruction is
not required.
Vector table. If the program changes an entry in the vector table, and then enables the corresponding
exception, use a DMB instruction between the operations. This ensures that if the exception is taken
immediately after being enabled the processor uses the new exception vector.
相关PDF资料 |
PDF描述 |
|---|---|
| HSC08DRYH-S13 | CONN EDGECARD 16POS .100 EXTEND |
| TH3D336M016A0600 | CAP TANT 33UF 16V 20% 2917 |
| GBA18DTKT-S288 | CONN EDGECARD 36POS .125 EXTEND |
| RSM03DRKN | CONN EDGECARD 6POS DIP .156 SLD |
| GBA22DRMI-S288 | CONN EDGECARD 44POS .125 EXTEND |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EFM32TG-STK3300 | 制造商:Energy Micro AS 功能描述:STARTER KIT STK3300 TINY GEC 制造商:Energy Micro AS 功能描述:STARTER KIT, STK3300, TINY GECKO; Silicon Manufacturer:Energy Micro; Core Architecture:ARM; Core Sub-Architecture:Cortex-M3; Silicon Core Number:EFM32TG840; Silicon Family Name:EFM32; Kit Contents:Starter Kit EFM32TG840; SVHC:No SVHC;RoHS Compliant: Yes |
| EFM32WG230F128 | 功能描述:ARM微控制器 - MCU 128kb flash 32kb RAM RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 处理器系列:STM32F373xx 数据总线宽度:32 bit 最大时钟频率:72 MHz 程序存储器大小:256 KB 数据 RAM 大小:32 KB 片上 ADC:Yes 工作电源电压:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:LQFP-48 安装风格:SMD/SMT |
| EFM32WG230F128-QFN64 | 制造商:Energy Micro AS 功能描述:32 BIT ARM MPU, WONDER GECKO - Tape and Reel 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 128KB FLASH 64QFN |
| EFM32WG230F128-QFN64T | 制造商:Energy Micro AS 功能描述:WONDER GECKO 32 BIT ARM CORTEX MCU - Trays |
| EFM32WG230F128-QFN64-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 128KB FLASH 64QFN |
发布紧急采购，3分钟左右您将得到回复。