参数资料
型号: EFM32-TG822F32-SK
厂商: Energy Micro
文件页数: 133/136页
文件大小: 0K
描述: IC MICRO KIT GECKO 48LQFP
标准包装: 1
系列: Tiny Gecko
套件类型: 微控制器
值: 2 件 - 闪存 - 32KB
包装: 纸板盒
安装类型: 表面贴装
包括封装: 48-LQFP
其它名称: 914-1023
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
96
www.energymicro.com
Bits
Name
Function
[2]
DISFOLD
When set to 1, disables IT folding. see Section 4.3.2.1 (p. 96) for more information.
[1]
DISDEFWBUF
When set to 1, disables write buffer use during default memory map accesses. This causes
all bus faults to be precise bus faults but decreases performance because any store to
memory must complete before the processor can execute the next instruction.
Note
This bit only affects write buffers implemented in the Cortex-M3 processor.
[0]
DISMCYCINT
When set to 1, disables interruption of load multiple and store multiple instructions. This
increases the interrupt latency of the processor because any LDM or STM must complete
before the processor can stack the current state and enter the interrupt handler.
4.3.2.1 About IT folding
In some situations, the processor can start executing the first instruction in an IT block while it is still
executing the IT instruction. This behavior is called IT folding, and improves performance, However, IT
folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit to 1 before executing
the task, to disable IT folding.
4.3.3 CPUID Base Register
The CPUID register contains the processor part number, version, and implementation information. See
the register summary in Table 4.12 (p. 94) for its attributes. The bit assignments are:
31
16 15
4 3
0
Im plem ent er
Revision
Part No
24 23
20 19
Variant
Const ant
Table 4.14. CPUID register bit assignments
Bits
Name
Function
[31:24]
Implementer
Implementer code:
0x41
= ARM
[23:20]
Variant
Variant number, the r value in the rnpn product revision identifier:
0x2
= r2pX
[19:16]
Constant
Reads as 0xF
[15:4]
PartNo
Part number of the processor:
0xC23
= Cortex-M3
[3:0]
Revision
Revision number, the p value in the rnpn product revision identifier:
0x0
= rXp0
0x1
= rXp1
4.3.4 Interrupt Control and State Register
The ICSR:
provides:
a set-pending bit for the Non-Maskable Interrupt (NMI) exception
set-pending and clear-pending bits for the PendSV and SysTick exceptions
indicates:
the exception number of the exception being processed
whether there are preempted active exceptions
the exception number of the highest priority pending exception
whether any interrupts are pending.
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