参数资料
型号: EFM32TG232F32
厂商: Energy Micro
文件页数: 129/136页
文件大小: 0K
描述: IC MCU 32BIT 32KB FLASH 64LQFP
特色产品: EFM32 Tiny Gecko
标准包装: 1
系列: Tiny Gecko
核心处理器: ARM? Cortex?-M3
芯体尺寸: 32-位
速度: 32MHz
连通性: I²C,IrDA,智能卡,SPI,UART/USART
外围设备: 欠压检测/复位,DMA,I²S,POR,PWM,WDT
输入/输出数: 53
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 4K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.8 V
数据转换器: A/D 8x12b,D/A 1x12b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 标准包装
其它名称: 914-1030-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
92
www.energymicro.com
ACTIVE bit s
31
0
Table 4.8. IABR bit assignments
Bits
Name
Function
[31:0]
ACTIVE
Interrupt active flags:
0 = interrupt not active
1 = interrupt active.
A bit reads as one if the status of the corresponding interrupt is active or active and pending.
4.2.7 Interrupt Priority Registers
The IPR0-IPRm registers provide an 3-bit priority field for each interrupt. These registers are byte-
accessible. See the register summary in Table 4.2 (p. 88) for their attributes. Each register holds
four priority fields, that map to four elements in the CMSIS interrupt priority array IP[0] to IP[n-1],
as shown:
IP[ n-1]
31
24 23
16 15
8 7
0
IP[ n-2]
IP[ n-3]
IPRm
IP[ 4k+ 3]
IP[ 4k+ 2]
IP[ 4k+ 1]
IP[ 4k]
IPRk
IP[ 3]
IP[ 2]
IP[ 1]
IP[ 0]
IPR0
.
Table 4.9. IPR bit assignments
Bits
Name
Function
[31:24]
Priority, byte offset 3
[23:16]
Priority, byte offset 2
[15:8]
Priority, byte offset 1
[7:0]
Priority, byte offset 0
Each priority field holds a priority value, 0-7. The lower the value, the greater the
priority of the corresponding interrupt. Only bits[7:5] of each field are implemented,
bits[4:0] read as zero and ignore writes.
See Section 4.2.1 (p. 89) for more information about the IP[0] to IP[n-1] interrupt priority array,
that provides the software view of the interrupt priorities.
Find the IPR number and byte offset for interrupt N (n, the maximum number for N is given by Table 1.1 (p.
5) and subtracted by 1) as follows:
the corresponding IPR number, k, is given by k = N DIV 4
the byte offset of the required Priority field in this register is N MOD 4, where:
byte offset 0 refers to register bits[7:0]
byte offset 1 refers to register bits[15:8]
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