参数资料
型号: EFM32TG232F32
厂商: Energy Micro
文件页数: 4/136页
文件大小: 0K
描述: IC MCU 32BIT 32KB FLASH 64LQFP
特色产品: EFM32 Tiny Gecko
标准包装: 1
系列: Tiny Gecko
核心处理器: ARM? Cortex?-M3
芯体尺寸: 32-位
速度: 32MHz
连通性: I²C,IrDA,智能卡,SPI,UART/USART
外围设备: 欠压检测/复位,DMA,I²S,POR,PWM,WDT
输入/输出数: 53
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 4K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.8 V
数据转换器: A/D 8x12b,D/A 1x12b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 标准包装
其它名称: 914-1030-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
101
www.energymicro.com
Bits
Name
Function
[4]
SEVONPEND
Send Event on Pending bit:
0 = only enabled interrupts or events can wakeup the processor, disabled interrupts are
excluded1 = enabled events and all interrupts, including disabled interrupts, can wakeup the
processor.
When an event or interrupt enters pending state, the event signal wakes up the processor
from WFE. If the processor is not waiting for an event, the event is registered and affects the
next WFE.
The processor also wakes up on execution of an SEV instruction or an external event.
[3]
-
Reserved.
[2]
SLEEPDEEP
Controls whether the processor uses sleep or deep sleep as its low power mode:
0 = sleep
1 = deep sleep.
[1]
SLEEPONEXIT
Indicates sleep-on-exit when returning from Handler mode to Thread mode:
0 = do not sleep when returning to Thread mode.
1 = enter sleep, or deep sleep, on return from an ISR.
Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main
application.
[0]
-
Reserved.
4.3.8 Configuration and Control Register
The CCR controls entry to Thread mode and enables:
the handlers for NMI, hard fault and faults escalated by FAULTMASK to ignore bus faults
trapping of divide by zero and unaligned accesses
access to the STIR by unprivileged software, see Section 4.2.8 (p. 93) .
See the register summary in Table 4.12 (p. 94) for the CCR attributes.
The bit assignments are:
DIV_0_TRP
Reserved
UNALIGN_TRP
NONBASETHRDENA
USERSETMPEND
BFHFNMIGN
STKALIGN
Reserved
31
10 9 8 7
5 4 3 2 1 0
Reserved
Table 4.20. CCR bit assignments
Bits
Name
Function
[31:10]
-
Reserved.
[9]
STKALIGN
Indicates stack alignment on exception entry:
0 = 4-byte aligned1 = 8-byte aligned.
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