参数资料
| 型号： | EL5126CLZ-T7 |
| 厂商： | Intersil |
| 文件页数： | 5/12页 |
| 文件大小： | 0K |
| 描述： | IC VOLTAGE GEN 8CH TFT-LCD 32QFN |
| 标准包装： | 1,000 |
| 应用： | 转换器，TFT，LCD |
| 输入电压： | 4.5 V ~ 16.5 V |
| 输出数： | 8 |
| 输出电压： | 0.5 V ~ 14.95 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x6） |
| 包装： | 带卷 (TR) |
EL5126
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - LPP EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
3
SCLK
SDA
2.5
2
2.857W
1.5
OUTPUT
1
0.5
0
M=400μs/DIV
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 9. SMALL SIGNAL RESPONSE (FALLING FROM
200mV TO 0V)
FIGURE 10. POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 AND SEMI G42-88
(SINGLE LAYER) TEST BOARD
0.8
0.7 758mW
0.6
0.5
0.4
0.3
0.2
0.1
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 11. POWER DISSIPATION vs AMBIENT TEMPERATURE
General Description
The EL5126 provides a versatile method of providing the
reference voltages that are used in setting the transfer
characteristics of LCD display panels. The V/T
(Voltage/Transmission) curve of the LCD panel requires that
a correction is applied to make it linear; however, if the panel
is to be used in more than one application, the final curve
may differ for different applications. By using the EL5126,
the V/T curve can be changed to optimize its characteristics
according to the required application of the display product.
Each of the eight reference voltage outputs can be set with a
10-bit resolution. These outputs can be driven to within
50mV of the power rails of the EL5126. As all of the output
buffers are identical, it is also possible to use the EL5126 for
applications other than LCDs where multiple voltage
references are required that can be set to 10 bit accuracy.
5
Digital Interface
The EL5126 uses a simple two-wire I 2 C digital interface to
program the outputs. The bus line SCLK is the clock signal
line and bus SDA is the data information signal line. The
EL5126 can support the clock rate up to 400kHz. External
pull up resistor is required for each bus line. The typical
value for these two pull up resistor is about 1k Ω .
START AND STOP CONDITION
The Start condition is a high to low transition on the SDA line
while SCLK is high. The Stop condition is a low to high
transition on the SDA line while SCLK is high. The start and
stop conditions are always generated by the master. The
bus is considered to be busy after the start condition and to
be free again a certain time after the stop condition. The two
bus lines must be high when the buses are not in use. The
I 2 C Timing Diagram 2 shows the format.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EL5127 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:2.5MHz 4, 8, 10 & 12 Channel Rail-to-Rail Buffers |
| EL5127_06 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:2.5MHz 4, 8, 10 & 12 Channel Rail-to-Rail Buffers |
| EL5127_07 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:2.5MHz 4, 8, 10 & 12 Channel Rail-to-Rail Buffers |
| EL512-75 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Logic IC |
| EL512-750 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Logic IC |
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