参数资料
| 型号： | EL5126CLZ-T7 |
| 厂商： | Intersil |
| 文件页数： | 6/12页 |
| 文件大小： | 0K |
| 描述： | IC VOLTAGE GEN 8CH TFT-LCD 32QFN |
| 标准包装： | 1,000 |
| 应用： | 转换器，TFT，LCD |
| 输入电压： | 4.5 V ~ 16.5 V |
| 输出数： | 8 |
| 输出电压： | 0.5 V ~ 14.95 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x6） |
| 包装： | 带卷 (TR) |
EL5126
DATA VALIDITY
The data on the SDA line must be stable during the high
period of the clock. The high or low state of the data line can
only change when the clock signal on the SCLK line is low.
BYTE FORMAT AND ACKNOWLEDGE
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
the eight outputs at one time. Two data bytes are required for
10-bit data for each channel output and there are total of 16
data bytes for 8 channels. Data in data byte 1 and 2 is for
channel A. Data in data byte 15 and 16 is for channel H. D9
to D0 are the 10-bit data for each channel. The unused bits
in the data byte are "don't care" and can be set to either one
or zero. See Table 1 for program sample for one channel
setting:
TABLE 1.
DATA
The master puts a resistive high level on the SDA line during
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CONDITION
the acknowledge clock pulse. The peripheral that
acknowledges has to pull down the SDA line during the
acknowledge clock pulse.
DEVICES ADDRESS AND W/R BIT
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Data value = 0
Data value = 512
Data value = 31
Data value = 1023
Data transfers follow the format shown in Timing Diagram 1.
After the Start condition, a first byte is sent which contains
the Device Address and write/read bit. This address is a 7-
bit long device address and only two device addresses (74H
and 75H) are allowed for the EL5126. The first 6 bits (A6 to
A1, MSBs) of the device address have been factory
programmed and are always 111010. Only the least
significant bit A0 is allowed to change the logic state, which
can be tied to VSD or DGND. A maximum of two EL5126
may be used on the same bus at one time. The EL5126
monitors the bus continuously and waiting for the start
condition followed by the device address. When a device
recognizes its device address, it will start to accept data. An
eighth bit is followed by the device address, which is a data
direction bit (W/R). A "0" indicates a Write transmission and
a "1" indicates a Read transmission.
The EL5126 can be operated as Standard mode and
Register mode. See the I 2 C Timing Diagram 1 for detail
formats.
STANDARD MODE
The part operates at Standard Mode if pin 28 (STD/REG) is
held high. The Standard Mode allows the user to program
TABLE 2.
When the W/R bit is high, the master can read the data from
the EL5126. See Timing Diagram 1 for detail formats.
REGISTER MODE
The part operates at Register Mode if pin 28 (STD/REG) is
held low. The Register Mode allows the user to program
each output individually. Followed by the first byte, the
second byte sets the register address for the programmed
output channel. Bits R0 to R3 set the output channel
address. For the unused bits in the R4 to R7 are "don't care".
See Table 2 for program sample.
The EL5126 also allows the user to read the data at Register
Mode. See Timing Diagram 1 for detail formats.
DIGITAL FILTER
A user selectable digital filter can be used to filter noise
spikes from the SCLK and SDA inputs. When the Filter pin
(pin27) is high, the digital filter is enabled. When the Filter
pin is low, the digital filter is disabled.
REGISTER ADDRESS
DATA
R3
X
X
X
X
R2
0
0
0
1
R1
0
0
1
1
R0
0
1
0
1
D9
0
1
0
1
D8
0
0
0
1
D7
0
0
0
1
D6
0
0
0
1
D5
0
0
0
1
D4
0
0
1
1
D3
0
0
1
1
D2
0
0
1
1
D1
0
0
1
1
D0
0
0
1
1
CONDITION
Channel A, Value = 0
Channel B, Value = 512
Channel C, Value = 31
Channel H, Value = 1023
6
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