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| 型号： | EM6617SO28A |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0°C to 70°C; Package: 8-EPSOIC T&R |
| 中文描述： | 微控制器 |
| 文件页数： | 32/67页 |
| 文件大小： | 824K |
| 代理商： | EM6617SO28A |
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EM6617
03/02 REV. C/442
Copyright
2002, EM Microelectronic-Marin SA
38
www.emmicroelectronic.com
12. Supply Voltage Level Detector
The EM6617 has a built-in Supply Voltage Level Detector (SVLD) circuitry, such that the CPU can compare the
supply voltage against a pre-selected value. During sleep mode this function is inhibited.
The CPU activates the supply voltage level
detector by writing VldStart = 1 in the register
RegVldCntl
. The actual measurement starts on
the next Ck[9] rising edge and lasts during the
Ck[9] high period (2 ms at 32 KHz). The busy
flag VldBusy stays high from VldStart set until
the measurement is finished. The worst case
time until the result is available is 1.5 Ck[9]
prescaler clock periods (32 KHz -> 6 ms). The
detection level must be defined in register
RegVldLevel
before the VldStart bit is set.
During the actual measurement (2 ms) the
device will draw an additional 5 A of IVDD
current. After the end of the measure the result
is available by inspection of the bit VldResult.
An interrupt IRQVLD is send to indicate the end
of measure. If the result is read 0, then the
power supply voltage was greater than the detection level value. If read 1, the power supply voltage was lower
than the detection level value. During each read while Busy=1 the VldResult is not guaranteed. The interrupt
request can be masked (default) (MaskIRQVLD bit).
12.1 SVLD Register
Table 12.1.1 register RegVldCntl
Bit
Name
Reset
R/W
Description
3
VLDResult
0
R*
Vld result flag
2
VLDStart
0
W
Vld start
2
VLDBusy
0
R
Vld busy flag
1
VLDlevel1
0
R/W
Vld level selection
0
VLDlevel0
0
R/W
Vld level selection
R*; VLDResult is not guaranteed while VLDBusy=1
Table 12.1.2 Voltage level detector value selecting
Level
VldLevel1
VldLevel0
Typical voltage level
Level1
0
2.2
Level2
0
1
2.5
Level3
1
0
3.0
Level3
1
3.0
Figure 28. SVLD Timing Diagram
VBAT =VDD
Compare Level
Ck[9] (256 Hz)
CPU starts
measure
Busy Flag
Measure
1
0
Result
Read Result
SVLD > VBAT
SVLD < VBAT
CPU starts
measure
相关PDF资料 |
PDF描述 |
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| EM6617SO28B | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 8-EPSOIC T&R |
| EM6617TP28A | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0°C to 70°C; Package: 8-EPSOIC T&R |
| EM6617TP28B | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 8-EPSOIC T&R |
| EM6640SO18A | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 8-SOIC |
| EM6640SO18B | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 10-DFN |
相关代理商/技术参数 |
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| EM6617SO28B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microcontroller |
| EM6617TP28A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microcontroller |
| EM6617TP28B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microcontroller |
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