参数资料
型号: EP1C6F144I7ES
厂商: Altera Corporation
英文描述: Cyclone FPGA Family Data Sheet
中文描述: 气旋的FPGA系列数据手册
文件页数: 35/104页
文件大小: 763K
代理商: EP1C6F144I7ES
Altera Corporation
January 2007
2–29
Preliminary
Global Clock Network & Phase-Locked Loops
Single-Port Mode
The M4K memory blocks also support single-port mode, used when
simultaneous reads and writes are not required. See
Figure 2–21
. A single
M4K memory block can support up to two single-port mode RAM blocks
if each RAM block is less than or equal to 2K bits in size.
Figure 2–21. Single-Port Mode
Note (1)
Note to
Figure 2–21
:
(1)
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
Global Clock
Network &
Phase-Locked
Loops
Cyclone devices provide a global clock network and up to two PLLs for a
complete clock management solution.
Global Clock Network
There are four dedicated clock pins (
CLK[3..0]
, two pins on the left side
and two pins on the right side) that drive the global clock network, as
shown in
Figure 2–22
. PLL outputs, logic array, and dual-purpose clock
(
DPCLK[7..0]
) pins can also drive the global clock network.
6
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
data[ ]
address[ ]
RAM/ROM
256
×
16
512
×
8
1,024
×
4
2,04
8
×
2
4,096
×
1
Data In
Address
Write Ena
b
le
Data O
u
t
o
u
tclken
inclken
inclock
o
u
tclock
Write
P
u
lse
Generator
w
ren
6 LAB Ro
w
Clocks
To M
u
ltiTrack
Interconnect
相关PDF资料
PDF描述
EP1C6F144I8ES Cyclone FPGA Family Data Sheet
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EP1C6F240C7ES Cyclone FPGA Family Data Sheet
EP1C6F240C8ES Cyclone FPGA Family Data Sheet
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