参数资料
型号: EP1C6T256I8ES
厂商: Altera Corporation
英文描述: Cyclone FPGA Family Data Sheet
中文描述: 气旋的FPGA系列数据手册
文件页数: 82/104页
文件大小: 763K
代理商: EP1C6T256I8ES
4–12
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
Table 4–22. IOE Internal Timing Microparameter Descriptions
Symbol
Parameter
t
SU
IOE input and output register setup time before clock
t
H
IOE input and output register hold time after clock
t
CO
IOE input and output register clock-to-output delay
t
PIN2COMBOUT_R
Row input pin to IOE combinatorial output
t
PIN2COMBOUT_C
Column input pin to IOE combinatorial output
t
COMBIN2PIN_R
Row IOE data input to combinatorial output pin
t
COMBIN2PIN_C
Column IOE data input to combinatorial output pin
t
CLR
Minimum clear pulse width
t
PRE
Minimum preset pulse width
t
CLKHL
Minimum clock high or low time
Table 4–23. M4K Block Internal Timing Microparameter Descriptions
Symbol
Parameter
t
M4KRC
Synchronous read cycle time
t
M4KWC
Synchronous write cycle time
t
M4KWERESU
W
rite or read enable setup time before clock
t
M4KWEREH
W
rite or read enable hold time after clock
t
M4KBESU
Byte enable setup time before clock
t
M4KBEH
Byte enable hold time after clock
t
M4KDATAASU
A port data setup time before clock
t
M4KDATAAH
A port data hold time after clock
t
M4KADDRASU
A port address setup time before clock
t
M4KADDRAH
A port address hold time after clock
t
M4KDATABSU
B port data setup time before clock
t
M4KDATABH
B port data hold time after clock
t
M4KADDRBSU
B port address setup time before clock
t
M4KADDRBH
B port address hold time after clock
t
M4KDATACO1
Clock-to-output delay when using output registers
t
M4KDATACO2
Clock-to-output delay without output registers
t
M4KCLKHL
Minimum clock high or low time
t
M4KCLR
Minimum clear pulse width
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