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参数资料
| 型号： | EP20K100BC356-2 |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 现场可编程门阵列（FPGA） |
| 文件页数： | 18/114页 |
| 文件大小： | 1623K |
| 代理商： | EP20K100BC356-2 |
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Copyright
2001 Altera Corporation. All rights reserved. AMMP, Altera, APEX, APEX 20K, APEX 20KE,
ByteBlaster, ClockBoost, ClockLock, ClockShift, EP20K30E, EP20K60E, EP20K100, EP20K100E, EP20K160E,
EP20K200, EP20K200E, EP20K300, EP20K400, EP20K400E, EP20K600E, EP20K1000E, EP20K1500E, FastTrack,
FineLine BGA, MasterBlaster, MegaCore, MegaLAB, MultiCore, MultiVolt, NativeLink, Quartus, Quartus II,
SignalTap and Turbo Bit are trademarks and/or service marks of Altera Corporation in the United States and
other countries. Altera acknowledges the trademarks of other organizations for their respective products or
services mentioned in this document. Altera products are protected under numerous U.S. and foreign patents
and pending applications, maskwork rights, and copyrights. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera’s
standard warranty, but reserves the right to make changes to any products and services at
any time without notice. Altera assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as
expressly agreed to in writing by Altera Corporation. Altera customers are advised to
obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Applications Hotline:
(800) 800-EPLD
Customer Marketing:
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Literature Services:
lit_req@altera.com
APEX 20K Programmable Logic Device Family Data Sheet
114
Altera Corporation
Printed on Recycled Paper.
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Updated Tables 114 and 115.
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Updated Timing Model section.
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Added Figure 37.
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Updated Figure 40.
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Updated Power Sequencing & Hot Socketing section.
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Updated Table 8.
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Included minor text changes.
Version 3.6 Changes
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Updated Figures 27 and 28.
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Updated Table 9.
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Included minor text changes.
Version 3.5 Changes
All preliminary information headings were removed from version 3.5.
Version 3.4 Changes
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| EP20K100BC356-3 | Field Programmable Gate Array (FPGA) |
| EP20K100BC356-3ES | FPGA |
| EP20K100BI356-1 | Field Programmable Gate Array (FPGA) |
| EP20K100EFC144-3ES | FPGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K100BC356-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100BC356-2N | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100BC356-2X | 制造商:Altera Corporation 功能描述:IC APEX 20K FPGA 356BGA 制造商:Altera Corporation 功能描述:IC FPGA 252 I/O 356BGA |
| EP20K100BC3563 | 制造商:ALTERA 功能描述:* |
| EP20K100BC356-3 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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