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| 型号： | EP20K100E |
| 厂商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family |
| 中文描述： | 可编程逻辑器件系列 |
| 文件页数： | 65/117页 |
| 文件大小： | 570K |
| 代理商： | EP20K100E |
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Altera Corporation
65
APEX 20K Programmable Logic Device Family Data Sheet
1
For DC Operating Specifications on APEX 20KE I/O standards,
please refer to
Application Note 117 (Using Selectable I/O Standards
in Altera Devices).
Notes to
Tables 27
through
30
:
(1)
See the
Operating Requirements for Altera Devices Data Sheet
.
(2)
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.75 V for
input currents less than 100 mA and periods shorter than 20 ns.
(3)
Numbers in parentheses are for industrial-temperature-range devices.
(4)
Maximum V
rise time is 100 ms, and V
must rise monotonically.
(5)
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to the voltage
shown in the following table based on input duty cycle for input currents less than 100 mA. The overshoot is
dependent upon duty cycle of the signal. The DC case is equivalent to 100% duty cycle.
Vin Max. Duty Cycle
4.0V 100% (DC)
4.1 90%
4.2 50%
4.3 30%
4.4 17%
4.5 10%
(6)
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V
CCINT
and V
CCIO
are
powered.
(7)
Typical values are for T
= 25
°
C, V
= 1.8 V, and V
= 1.8 V, 2.5 V or 3.3 V.
(8)
These values are specified under the APEX 20KE device recommended operating conditions, shown in Table 24 on
page 60.
(9)
Refer to
Application Note 117 (Using Selectable I/O Standards in Altera Devices)
for the V
IH
, V
IL
, V
OH
, V
OL
, and I
I
parameters when VCCIO = 1.8 V.
(10) The APEX 20KE input buffers are compatible with 1.8-V, 2.5-V and 3.3-V (LVTTL and LVCMOS) signals.
Additionally, the input buffers are 3.3-V PCI compliant. Input buffers also meet specifications for GTL+, CTT, AGP,
SSTL-2, SSTL-3, and HSTL.
(11) The I
OH
parameter refers to high-level TTL, PCI, or CMOS output current.
(12) The I
parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
as well as output pins.
(13) This value is specified for normal device operation. The value may vary during power-up.
(14) Pin pull-up resistance values will be lower if an external source drives the pin higher than V
CCIO
.
(15) Capacitance is sample-tested only.
Figure 33
shows the relationship between V
CCIO
and V
CCINT
for 3.3-V PCI
compliance on APEX 20K devices.
Table 30. APEX 20KE Device Capacitance
Note (15)
Symbol
Parameter
Conditions
Min
Max
Unit
C
IN
C
INCLK
Input capacitance
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
8
pF
Input capacitance on
dedicated clock pin
12
pF
C
OUT
Output capacitance
V
OUT
= 0 V, f = 1.0 MHz
8
pF
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K100EBC356-1 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 246 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100EBC356-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EBC356-1X | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 246 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100EBC356-2 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 246 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100EBC356-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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