- 您现在的位置：买卖IC网 > PDF目录299031 > EP20K100EFC400-3 (ALTERA CORP) LOADABLE PLD, PBGA400 PDF资料下载
参数资料
| 型号： | EP20K100EFC400-3 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA400 |
| 文件页数： | 41/65页 |
| 文件大小： | 781K |
| 代理商： | EP20K100EFC400-3 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页当前第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页
68
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
In addition, two PLLs include special circuitry to support T1/E1
conversion. The T1 telecommunications standard uses a 1.544-MHz clock,
and the E1 telecommunications standard uses a 2.048-MHz clock. These
two PLLs can convert a T1 clock to an E1 clock, or vice versa.
Clock Phase & Delay Adjustment
The APEX 20KE ClockShift feature allows the clock phase and delay to be
adjusted. The clock phase can be adjusted by 90 steps. The clock delay can
be adjusted to increase or decrease the clock delay by approximately 2 ns
with 0.5-ns resolution.
LVDS Support
Two PLLs are designed to support the LVDS interface. When using LVDS,
the I/O clock runs at a slower rate than the data transfer rate. Thus, PLLs
are used to multiply the I/O clock internally to capture the LVDS data.
For example, an I/O clock may run at 50 MHz to support
400 Mbits/second LVDS data transfer. In this example, the PLL multiplies
the incoming clock by 8 to support the high-speed data transfer. The
LVDS interface is supported by EP20K300E and larger devices.
The APEX 20KE ClockLock circuitry supports individual LOCK signals.
The LOCK signal drives high when the ClockLock circuit has locked onto
the input clock. Both signals are optional for each ClockLock circuit; when
not used, they are I/O pins.
ClockLock & ClockBoost Timing Parameters
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock during configuration. The circuit will be ready for use immediately
after configuration. Figure 31 shows the incoming and generated clock
specifications.
相关PDF资料 |
PDF描述 |
|---|---|
| EP20K100EFI400-1 | LOADABLE PLD, PBGA400 |
| EP20K100EFI400-2 | LOADABLE PLD, PBGA400 |
| EP20K100EFI400-3 | LOADABLE PLD, PBGA400 |
| EP20K100EFC784-1 | LOADABLE PLD, PBGA784 |
| EP20K100EFC784-2 | LOADABLE PLD, PBGA784 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K100EFI144-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EFI144-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EFI144-2X | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100EFI144-3ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EFI324-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
发布紧急采购，3分钟左右您将得到回复。