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| 型号： | EP20K100EFC400-3 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA400 |
| 文件页数： | 44/65页 |
| 文件大小： | 781K |
| 代理商： | EP20K100EFC400-3 |
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Altera Corporation
71
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
The APEX 20K device instruction register length is 10 bits. The APEX 20K
boundary-scan register length and device IDCODE information for
APEX 20K devices.
Note:
(1)
Consult Altera Applications for up-to-date information on this device.
Table 11. APEX 20K JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern to be output at the device pins.
Also used by the SignalTap embedded logic analyzer.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a test
pattern at the output pins and capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operation.
USERCODE
Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE to be serially shifted out of TDO.
IDCODE
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE
to be serially shifted out of TDO.
ICR Instructions
These instructions are used when configuring an APEX 20K device via the JTAG port with
a ByteBlasterMV download cable, or using a Jam File or Jam Byte-Code File via an
embedded processor.
SignalTap
Instructions
These instructions monitor internal device operation with the SignalTap embedded logic
analyzer.
Table 12. APEX 20K Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EP20K100
EP20K100E
EP20K160E
EP20K200
EP20K200E
EP20K300E
EP20K400
1,536
EP20K400E
EP20K600E
EP20K1000E
相关PDF资料 |
PDF描述 |
|---|---|
| EP20K100EFI400-1 | LOADABLE PLD, PBGA400 |
| EP20K100EFI400-2 | LOADABLE PLD, PBGA400 |
| EP20K100EFI400-3 | LOADABLE PLD, PBGA400 |
| EP20K100EFC784-1 | LOADABLE PLD, PBGA784 |
| EP20K100EFC784-2 | LOADABLE PLD, PBGA784 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K100EFI144-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EFI144-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EFI144-2X | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100EFI144-3ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EFI324-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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