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参数资料
| 型号： | EP20K100EQI208-2ES |
| 元件分类： | 数字电位计 |
| 英文描述： | Digitally Controlled Potentiometer (XDCP™), Terminal Voltage ±2.7V to ±5V, 128 Taps, Up/Down Interface; Temperature Range: -40°C to 85°C; Package: 10-MSOP |
| 中文描述： | FPGA的 |
| 文件页数： | 54/114页 |
| 文件大小： | 1623K |
| 代理商： | EP20K100EQI208-2ES |
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Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Advanced I/O Standard Support
APEX 20KE IOEs support the following I/O standards: LVTTL,
LVCMOS, 1.8-V I/O, 2.5-V I/O, 3.3-V PCI, PCI-X, 3.3-V AGP, LVDS,
LVPECL, GTL+, CTT, HSTL Class I, SSTL-3 Class I and II, and SSTL-2
Class I and II.
f For more information on I/O standards supported by APEX 20KE
devices, see Application Note 117 (Using Selectable I/O Standards in Altera
Devices).
The APEX 20KE device contains eight I/O banks. In QFP packages, the
banks are linked to form four I/O banks. The I/O banks directly support
all standards except LVDS and LVPECL. All I/O banks can support LVDS
and LVPECL with the addition of external resistors. In addition, one block
within a bank contains circuitry to support high-speed True-LVDS and
LVPECL inputs, and another block within a particular bank supports
high-speed True-LVDS and LVPECL outputs. The LVDS blocks support
all of the I/O standards. Each I/O bank has its own VCCIO pins. A single
device can support 1.8-V, 2.5-V, and 3.3-V interfaces; each bank can
support a different standard independently. Each bank can also use a
separate VREF level so that each bank can support any of the terminated
standards (such as SSTL-3) independently. Within a bank, any one of the
terminated standards can be supported. EP20K300E and larger
APEX 20KE devices support the LVDS interface for data pins (smaller
devices support LVDS clock pins, but not data pins). All EP20K300E and
larger devices support the LVDS interface for data pins up to 155 Mbit per
channel; EP20K400E devices and larger with an X-suffix on the ordering
code add a serializer/deserializer circuit and PLL for higher-speed
support.
Each bank can support multiple standards with the same VCCIO for
output pins. Each bank can support one voltage-referenced I/O standard,
but it can support multiple I/O standards with the same VCCIO voltage
level. For example, when VCCIO is 3.3 V, a bank can support LVTTL,
LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
When the LVDS banks are not used as LVDS I/O banks, they support all
of the other I/O standards. Figure 29 shows the arrangement of the
APEX 20KE I/O banks.
相关PDF资料 |
PDF描述 |
|---|---|
| EP20K100EQI208-3ES | FPGA |
| EP20K100EQI240-1ES | FPGA |
| EP20K100EQI240-2ES | Digitally Controlled Potentiometer (XDCP™) Terminal Voltage ±2.7V or ±5V, 128 Taps I2C Serial Interface; Temperature Range: -40°C to 85°C; Package: 10-MSOP T&R |
| EP20K100EQI240-3ES | FPGA |
| EP20K100ERC208-1ES | Digitally Controlled Potentiometer (XDCP™) Terminal Voltage ±2.7V or ±5V, 128 Taps I2C Serial Interface; Temperature Range: -40°C to 85°C; Package: 10-MSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K100EQI208-3ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EQI240-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EQI240-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EQI240-2X | 功能描述:IC APEX 20KE FPGA 100K 240-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:APEX-20K® 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| EP20K100EQI240-3ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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