参数资料
型号: EP20K100EQI208-2ES
元件分类: 数字电位计
英文描述: Digitally Controlled Potentiometer (XDCP™), Terminal Voltage ±2.7V to ±5V, 128 Taps, Up/Down Interface; Temperature Range: -40°C to 85°C; Package: 10-MSOP
中文描述: FPGA的
文件页数: 57/114页
文件大小: 1623K
代理商: EP20K100EQI208-2ES
Altera Corporation
47
APEX 20K Programmable Logic Device Family Data Sheet
APEX 20KE devices also support the MultiVolt I/O interface feature. The
APEX 20KE VCCINT pins must always be connected to a 1.8-V power
supply. With a 1.8-V VCCINT level, input pins are 1.8-V, 2.5-V, and 3.3-V
tolerant. The VCCIO pins can be connected to either a 1.8-V, 2.5-V, or 3.3-V
power supply, depending on the I/O standard requirements. When the
VCCIO
pins are connected to a 1.8-V power supply, the output levels are
compatible with 1.8-V systems. When VCCIO pins are connected to a 2.5-V
power supply, the output levels are compatible with 2.5-V systems. When
VCCIO
pins are connected to a 3.3-V power supply, the output high is
3.3 V and compatible with 3.3-V or 5.0-V systems. An APEX 20KE device
is 5.0-V tolerant with the addition of a resistor.
Table 13 summarizes APEX 20KE MultiVolt I/O support.
Notes:
(1)
The PCI clamping diode must be disabled to drive an input with voltages higher than VCCIO, except for the 5.0-V
input case.
(2)
An APEX 20KE device can be made 5.0-V tolerant with the addition of an external resistor.
(3)
When VCCIO = 3.3 V, an APEX 20KE device can drive a 2.5-V device with 3.3-V tolerant inputs.
ClockLock &
ClockBoost
Features
APEX 20K devices support the ClockLock and ClockBoost clock
management features, which are implemented with PLLs. The ClockLock
circuitry uses a synchronizing PLL that reduces the clock delay and skew
within a device. This reduction minimizes clock-to-output and setup
times while maintaining zero hold times. The ClockBoost circuitry, which
provides a clock multiplier, allows the designer to enhance device area
efficiency by sharing resources within the device. The ClockBoost
circuitry allows the designer to distribute a low-speed clock and multiply
that clock on-device. APEX 20K devices include a high-speed clock tree;
unlike ASICs, the user does not have to design and optimize the clock tree.
The ClockLock and ClockBoost features work in conjunction with the
APEX 20K device’s high-speed clock to provide significant improvements
in system performance and band-width. Devices with an X-suffix on the
ordering code include the ClockLock circuit.
The ClockLock and ClockBoost features in APEX 20K devices are enabled
through the Quartus II software. External devices are not required to use
these features.
Table 13. APEX 20KE MultiVolt I/O Support
VCCIO (V)
Input Signals (V)
Output Signals (V)
1.8
2.5
3.3
5.0
1.8
2.5
3.3
5.0
1.8
vv (1)
v
2.5
v
3.3
vv
v (2)
vv
相关PDF资料
PDF描述
EP20K100EQI208-3ES FPGA
EP20K100EQI240-1ES FPGA
EP20K100EQI240-2ES Digitally Controlled Potentiometer (XDCP™) Terminal Voltage ±2.7V or ±5V, 128 Taps I2C Serial Interface; Temperature Range: -40°C to 85°C; Package: 10-MSOP T&R
EP20K100EQI240-3ES FPGA
EP20K100ERC208-1ES Digitally Controlled Potentiometer (XDCP™) Terminal Voltage ±2.7V or ±5V, 128 Taps I2C Serial Interface; Temperature Range: -40°C to 85°C; Package: 10-MSOP
相关代理商/技术参数
参数描述
EP20K100EQI208-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K100EQI240-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K100EQI240-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K100EQI240-2X 功能描述:IC APEX 20KE FPGA 100K 240-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:APEX-20K® 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA(34.55x34.55)
EP20K100EQI240-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA