参数资料
型号: EP20K100EQI208-2ES
元件分类: 数字电位计
英文描述: Digitally Controlled Potentiometer (XDCP™), Terminal Voltage ±2.7V to ±5V, 128 Taps, Up/Down Interface; Temperature Range: -40°C to 85°C; Package: 10-MSOP
中文描述: FPGA的
文件页数: 56/114页
文件大小: 1623K
代理商: EP20K100EQI208-2ES
46
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
MultiVolt I/O
Interface
The APEX device architecture supports the MultiVolt I/O interface
feature, which allows APEX devices in all packages to interface with
systems of different supply voltages. The devices have one set of VCC pins
for internal operation and input buffers (VCCINT), and another set for I/O
output drivers (VCCIO).
The APEX 20K VCCINT pins must always be connected to a 2.5 V power
supply. With a 2.5-V VCCINT level, input pins are 2.5-V and 3.3-V tolerant.
Certain devices, identified by a “V” suffix following the speed grade in the
ordering code (e.g., EP20K400BC652-1V), are 5.0-V tolerant. The VCCIO
pins can be connected to either a 2.5-V or 3.3-V power supply, depending
on the output requirements. When VCCIO pins are connected to a 2.5-V
power supply, the output levels are compatible with 2.5-V systems. When
the VCCIO pins are connected to a 3.3-V power supply, the output high is
3.3 V and is compatible with 3.3-V or 5.0-V systems.
Table 12 summarizes 5.0-V tolerant APEX 20K MultiVolt I/O support.
Notes:
(1)
The PCI clamping diode must be disabled to drive an input with voltages higher
than VCCIO.
(2)
APEX 20K devices with a “V” suffix are 5.0-V tolerant.
(3)
When VCCIO = 3.3 V, an APEX 20K device can drive a 2.5-V device with 3.3-V
tolerant inputs.
Open-drain output pins on 5.0-V tolerant APEX 20K devices (with a pull-
up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that
require a VIH of 3.5 V. When the pin is inactive, the trace will be pulled up
to 5.0 V by the resistor. The open-drain pin will only drive low or tri-state;
it will never drive high. The rise time is dependent on the value of the pull-
up resistor and load impedance. The IOL current specification should be
considered when selecting a pull-up resistor.
Table 12. 5.0-V Tolerant APEX 20K MultiVolt I/O Support
VCCIO (V)
Input Signals (V)
Output Signals (V)
2.5
3.3
5.0
2.5
3.3
5.0
2.5
vv(1)
v
3.3
vv
vv
相关PDF资料
PDF描述
EP20K100EQI208-3ES FPGA
EP20K100EQI240-1ES FPGA
EP20K100EQI240-2ES Digitally Controlled Potentiometer (XDCP™) Terminal Voltage ±2.7V or ±5V, 128 Taps I2C Serial Interface; Temperature Range: -40°C to 85°C; Package: 10-MSOP T&R
EP20K100EQI240-3ES FPGA
EP20K100ERC208-1ES Digitally Controlled Potentiometer (XDCP™) Terminal Voltage ±2.7V or ±5V, 128 Taps I2C Serial Interface; Temperature Range: -40°C to 85°C; Package: 10-MSOP
相关代理商/技术参数
参数描述
EP20K100EQI208-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K100EQI240-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K100EQI240-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K100EQI240-2X 功能描述:IC APEX 20KE FPGA 100K 240-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:APEX-20K® 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA(34.55x34.55)
EP20K100EQI240-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA