参数资料
型号: EP20K30EFI144-3ES
英文描述: FPGA
中文描述: FPGA的
文件页数: 67/114页
文件大小: 1623K
代理商: EP20K30EFI144-3ES
56
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
The APEX 20K device instruction register length is 10 bits. The APEX 20K
device USERCODE register length is 32 bits. Tables 20 and 21 show the
boundary-scan register length and device IDCODE information for
APEX 20K devices.
Note:
(1)
This device does not support JTAG boundary scan testing.
Table 20. APEX 20K Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EP20K30E
420
EP20K60E
624
EP20K100
786
EP20K100E
774
EP20K160E
984
EP20K200
1,176
EP20K200E
1,164
EP20K300E
1,266
EP20K400
1,536
EP20K400E
1,506
EP20K600E
1,806
EP20K1000E
2,190
EP20K1500E
1 (1)
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