参数资料
型号: EP20K400FC672-2
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 现场可编程门阵列(FPGA)
文件页数: 53/114页
文件大小: 1623K
代理商: EP20K400FC672-2
Altera Corporation
43
APEX 20K Programmable Logic Device Family Data Sheet
Figure 28 shows how a column IOE connects to the interconnect.
Figure 28. Column IOE Connection to the Interconnect
Dedicated Fast I/O Pins
APEX 20KE devices incorporate an enhancement to support bidirectional
pins with high internal fanout such as PCI control signals. These pins are
called Dedicated Fast I/O pins (FAST1, FAST2, FAST3, and FAST4) and
replace dedicated inputs. These pins can be used for fast clock, clear, or
high fanout logic signal distribution. They also can drive out. The
Dedicated Fast I/O pin data output and tri-state control are driven by
local interconnect from the adjacent MegaLAB for high speed.
Row Interconnect
Column Interconnect
Each IOE can drive column interconnect. In APEX 20KE devices,
IOEs can also drive FastRow interconnect. Each IOE data
and OE signal is driven by local interconnect.
Any LE or ESB can drive
a column pin through a
row, column, and MegaLAB
interconnect.
IOE
LAB
An LE or ESB can drive a
pin through a local
interconnect for faster
clock-to-output times.
MegaLAB Interconnect
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相关代理商/技术参数
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EP20K400FC672-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K400FC672-3 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 1664 Macro 502 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP20K400FC672-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K400FC672-3V 制造商:Rochester Electronics LLC 功能描述:- Bulk
EP20K400FI672-1 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA)