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| 型号： | EP20K400FC672-3ES |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件页数： | 74/114页 |
| 文件大小： | 1623K |
| 代理商： | EP20K400FC672-3ES |
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62
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
See the Operating Requirements for Altera Devices Data Sheet.
(2)
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns.
(3)
Numbers in parentheses are for industrial-temperature-range devices.
(4)
Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5)
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(6)
Typical values are for TA = 25° C, VCCINT = 2.5 V, and VCCIO = 2.5 V or 3.3 V.
(7)
These values are specified under the APEX 20K device recommended operating conditions, shown in Table 24 on
page 60.
(8)
The APEX 20K input buffers are compatible with 2.5-V and 3.3-V (LVTTL and LVCMOS) signals. Additionally, the
input buffers are 3.3-V PCI compliant when VCCIO and VCCINT meet the relationship shown in Figure 33 on page 68.
(9)
The IOH parameter refers to high-level TTL, PCI, or CMOS output current.
(10) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
as well as output pins.
(11) This value is specified for normal device operation. The value may vary during power-up.
(12) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO.
(13) Capacitance is sample-tested only.
recommended operating conditions, DC operating conditions, and
capacitance for 5.0-V tolerant APEX 20K devices. These devices are
identified by a “V” suffix following the speed grade in the ordering code
(e.g., EP20K400BC652-1V).
Table 27. APEX 20K 5.0-V Tolerant Device Absolute Maximum Ratings
Symbol
Parameter
Conditions
Min
Max
Unit
VCCINT
Supply voltage
With respect to ground (2)
–0.5
3.6
V
VCCIO
–0.5
4.6
V
VI
DC input voltage
–2.0
5.75
V
IOUT
DC output current, per pin
–25
25
mA
TSTG
Storage temperature
No bias
–65
150
° C
TAMB
Ambient temperature
Under bias
–65
135
° C
TJ
Junction temperature
PQFP, RQFP, TQFP, and BGA packages,
under bias
135
° C
Ceramic PGA packages, under bias
150
° C
相关PDF资料 |
PDF描述 |
|---|---|
| EP20K400FI672-1 | Field Programmable Gate Array (FPGA) |
| EP20K400FI672-1ES | FPGA |
| EP20K400FI672-2 | Field Programmable Gate Array (FPGA) |
| EP20K100QC240-3ES | Boost + VON Slice + VCOM; Temperature Range: -40°C to 85°C; Package: 24-QFN T&R |
| EP20K100QI208-1 | Boost + LDO + VON Slice + VCOM; Temperature Range: -40°C to 85°C; Package: 24-QFN T&R |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K400FC672-3V | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP20K400FI672-1 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP20K400FI672-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K400FI672-2 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP20K400FI672-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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