参数资料
型号: EP4CGX30CF23I7
厂商: Altera
文件页数: 31/42页
文件大小: 0K
描述: IC CYCLONE IV GX FPGA 30K 484FBG
产品培训模块: Cyclone IV FPGA Family Overview
特色产品: Cyclone? IV FPGAs
标准包装: 60
系列: CYCLONE® IV GX
LAB/CLB数: 1840
逻辑元件/单元数: 29440
RAM 位总计: 1105920
输入/输出数: 290
电源电压: 1.16 V ~ 1.24 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 484-BGA
供应商设备封装: 484-FBGA(23x23)
Chapter 1: Cyclone IV Device Datasheet
1–37
I/O Timing
December 2013
Altera Corporation
I/O Timing
Use the following methods to determine I/O timing:
the Excel-based I/O Timing
the Quartus II timing analyzer
The Excel-based I/O timing provides pin timing performance for each device density
and speed grade. The data is typically used prior to designing the FPGA to get a
timing budget estimation as part of the link timing analysis. The Quartus II timing
analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after place-and-route is complete.
f The Excel-based I/O Timing spreadsheet is downloadable from Cyclone IV Devices
Literature website.
Glossary
Table 1–46 lists the glossary for this chapter.
Table 1–46. Glossary (Part 1 of 5)
Letter
Term
Definitions
A
——
B
——
C
——
D
——
E
——
F
fHSCLK
High-speed I/O block: High-speed receiver/transmitter input and output clock frequency.
G
GCLK
Input pin directly to Global Clock network.
GCLK PLL
Input pin to Global Clock network through the PLL.
H
HSIODR
High-speed I/O block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
I
Input Waveforms
for the SSTL
Differential I/O
Standard
V
IL
V
REF
V
IH
VSWING
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EP4CGX30CF23I7N 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone IV GX 1840 LABs 290 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP4CGX30F17C8 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV Device Datasheet
EP4CGX30F23C8N 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV FPGA Device Faily Overview
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