参数资料
| 型号： | EP4CGX30CF23I7 |
| 厂商： | Altera |
| 文件页数： | 35/42页 |
| 文件大小： | 0K |
| 描述： | IC CYCLONE IV GX FPGA 30K 484FBG |
| 产品培训模块： | Cyclone IV FPGA Family Overview |
| 特色产品： | Cyclone? IV FPGAs |
| 标准包装： | 60 |
| 系列： | CYCLONE® IV GX |
| LAB/CLB数： | 1840 |
| 逻辑元件/单元数： | 29440 |
| RAM 位总计： | 1105920 |
| 输入/输出数： | 290 |
| 电源电压： | 1.16 V ~ 1.24 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 484-BGA |
| 供应商设备封装： | 484-FBGA（23x23） |
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Chapter 1: Cyclone IV Device Datasheet
Glossary
December 2013
Altera Corporation
T
tC
High-speed receiver and transmitter input and output clock period.
Channel-to-
channel-skew
(TCCS)
High-speed I/O block: The timing difference between the fastest and slowest output edges,
including tCO variation and clock skew. The clock is included in the TCCS measurement.
tcin
Delay from the clock pad to the I/O input register.
tCO
Delay from the clock pad to the I/O output.
tcout
Delay from the clock pad to the I/O output register.
tDUTY
High-speed I/O block: Duty cycle on high-speed transmitter output clock.
tFALL
Signal high-to-low transition time (80–20%).
tH
Input register hold time.
Timing Unit
Interval (TUI)
High-speed I/O block: The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
tINJITTER
Period jitter on the PLL clock input.
tOUTJITTER_DEDCLK
Period jitter on the dedicated clock output driven by a PLL.
tOUTJITTER_IO
Period jitter on the general purpose I/O driven by a PLL.
tpllcin
Delay from the PLL inclk pad to the I/O input register.
tpllcout
Delay from the PLL inclk pad to the I/O output register.
Transmitter
Output
Waveform
Transmitter output waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O
Standards:
tRISE
Signal low-to-high transition time (20–80%).
tSU
Input register setup time.
U
——
Table 1–46. Glossary (Part 4 of 5)
Letter
Term
Definitions
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Positive Channel (p) = V
OH
Negative Channel (n) = V
OL
Ground
VOD
V
OD
V
OD
0 V
Vos
p
- n
相关PDF资料 |
PDF描述 |
|---|---|
| AMM22DTAN-S189 | CONN EDGECARD 44POS R/A .156 SLD |
| AMM22DTAH-S189 | CONN EDGECARD 44POS R/A .156 SLD |
| EP4CGX30CF23C6 | IC CYCLONE IV GX FPGA 30K 484FBG |
| A54SX16-1PQG208 | IC FPGA SX 24K GATES 208-PQFP |
| A54SX16-PQ208I | IC FPGA SX 24K GATES 208-PQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP4CGX30CF23I7N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone IV GX 1840 LABs 290 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4CGX30F17C8 | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
| EP4CGX30F23C8N | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV FPGA Device Faily Overview |
| EP4CGX30F23I7N | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
| EP4CGX50 | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV FPGA Device Family Overview |
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