参数资料
型号: EP4SE530H35C3
厂商: Altera
文件页数: 46/82页
文件大小: 0K
描述: IC STRATIX IV FPGA 530K 1152HBGA
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 3
系列: STRATIX® IV E
LAB/CLB数: 21248
逻辑元件/单元数: 531200
RAM 位总计: 28033024
输入/输出数: 744
电源电压: 0.87 V ~ 0.93 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 1152-BBGA 裸露焊盘
供应商设备封装: 1152-HBGA(40x40)
1–42
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Stratix IV Device Handbook
March 2014
Altera Corporation
Volume 4: Device Datasheet and Addendum
Random jitter at
6.0 Gbps (G3)
Pattern = CJPAT
0.15
0.15
0.15
UI
SAS Receiver Jitter Tolerance (17)
Total Jitter tolerance at
1.5 Gbps (G1)
Pattern = CJPAT
> 0.65
UI
Deterministic Jitter
tolerance at 1.5 Gbps
(G1)
Pattern = CJPAT
> 0.35
UI
Sinusoidal Jitter
tolerance at 1.5 Gbps
(G1)
Jitter Frequency = 900
KHz to 5 MHz
Pattern = CJTPAT BER =
1E-12
> 0.1
UI
CPRI Transmit Jitter Generation (18)
Total Jitter
E.6.HV, E.12.HV
Pattern = CJPAT
0.279
0.279
0.279
UI
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Pattern = CJTPAT
0.35
0.35
0.35
UI
Deterministic Jitter
E.6.HV, E.12.HV
Pattern = CJPAT
0.14
0.14
0.14
UI
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Pattern = CJTPAT
0.17
0.17
0.17
UI
CPRI Receiver Jitter Tolerance (18)
Total jitter tolerance
E.6.HV, E.12.HV
Pattern = CJPAT
> 0.66
UI
Deterministic jitter
tolerance
E.6.HV, E.12.HV
Pattern = CJPAT
> 0.4
UI
Total jitter tolerance
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Pattern = CJTPAT
> 0.65
UI
Deterministic jitter
tolerance
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Pattern = CJTPAT
> 0.37
UI
Combined deterministic
and random jitter
tolerance
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Pattern = CJTPAT
> 0.55
UI
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1), (2) (Part 7 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
–3 Commercial/
Industrial
and –2× Commercial
Speed Grade
–3 Military (3) and
–4 Commercial/
Industrial Speed
Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
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