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参数资料
型号： EP7309-CV
厂商： Cirrus Logic Inc
文件页数： 25/42页
文件大小： 0K
描述： IC ARM720T MCU 74MHZ 208-LQFP
标准包装： 36
系列： EP7
核心处理器： ARM7
芯体尺寸： 32-位
速度： 74MHz
连通性： 编解码器，DAI，EBI/EMI，IrDA，键盘，SPI/Microwire1，UART/USART
外围设备： LCD，LED，MaverickKey，POR，PWM
输入/输出数： 27
程序存储器类型： ROMless
RAM 容量： 56K x 8
电压 - 电源 (Vcc/Vdd)： 2.3 V ~ 2.7 V
振荡器型： 外部
工作温度： 0°C ~ 70°C
封装/外壳： 208-LQFP
包装： 托盘
其它名称： 598-1213
DS507F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
31
EP7309
High-Performance, Low-Power System on Chip
B7
DD[2]
O
LCD serial display data
B8
CL[1]
O
LCD line clock
B9
VDDCORE
Core power
Digital core power, 2.5V
B10
D[1]
I/O
Data I/O
B11
A[2]
O
System byte address
B12
A[4]
O
System byte address
B13
A[5]
O
System byte address
B14
WAKEUP
I
System wake up input
B15
VDDIO
Pad power
Digital I/O power, 3.3V
B16
nURESET
I
User reset input
C1
VDDIO
Pad power
Digital I/O power, 3.3V
C2
EXPCLK
I
Expansion clock input
C3
VSSIO
Pad ground
I/O ground
C4
VDDIO
Pad power
Digital I/O power, 3.3V
C5
VSSIO
Pad ground
I/O ground
C6
VSSIO
Pad ground
I/O ground
C7
VSSIO
Pad ground
I/O ground
C8
VDDIO
Pad power
Digital I/O power, 3.3V
C9
VSSIO
Pad ground
I/O ground
C10
VSSIO
Pad ground
I/O ground
C11
VSSIO
Pad ground
I/O ground
C12
VDDIO
Pad power
Digital I/O power, 3.3V
C13
VSSIO
Pad ground
I/O ground
C14
VSSIO
Pad ground
I/O ground
C15
nPOR
I
Power-on reset input
C16
nEXTPWR
I
External power supply sense input
D1
WRITE
O
Transfer direction
D2
EXPRDY
I
Expansion port ready input
D3
VSSIO
Pad ground
I/O ground
D4
VDDIO
Pad power
Digital I/O power, 3.3V
D5
nCS[2]
O
Chip select out
D6
nMWE
O
ROM, expansion write enable
D7
N/C
O
D8
CL[2]
O
LCD pixel clock out
D9
VSSRTC
Core ground Real time clock ground
D10
D[4]
I/O
Data I/O
D11
nPWRFL
I
Power fail sense input
D12
MOSCIN
I
Main oscillator input
D13
VDDIO
Pad power
Digital I/O power, 3.3V
D14
VSSIO
Pad ground
I/O ground
D15
D[7]
I/O
Data I/O
D16
D[8]
I/O
Data I/O
E1
RXD[2]
I
UART 2 receive data input
E2
PB[7]
I
GPIO port B
E3
TDI
I
JTAG data input
E4
WORD
O
Word access select output
E5
VSSIO
Pad ground
I/O ground
E6
nCS[0]
O
Chip select out
Table 20. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Type
Description
E7
N/C
O
E8
FRM
O
LCD frame synchronization pulse
E9
A[0]
O
System byte address
E10
D[5]
I/O
Data I/O
E11
VSSOSC
Oscillator
ground
PLL ground
E12
VSSIO
Pad ground
I/O ground
E13
nMEDCHG/nBROM
I
Media change interrupt input / internal
rom boot enable
E14
VDDIO
Pad power
Digital I/O power, 3.3V
E15
D[9]
I/O
Data I/O
E16
D[10]
I/O
Data I/O
F1
PB[5]
I
GPIO port B
F2
PB[3]
I
GPIO port B
F3
VSSIO
Pad ground
I/O ground
F4
TXD[2]
O
UART 2 transmit data output
F5
RUN/CLKEN
O
Run output / clock enable output
F6
VSSIO
Pad ground
I/O ground
F7
N/C
O
F8
DD[3]
O
LCD serial display data
F9
A[1]
O
System byte address
F10
D[6]
I/O
Data I/O
F11
VSSRTC
RTC ground Real time clock ground
F12
BATOK
I
Battery ok input
F13
nBATCHG
I
Battery changed sense input
F14
VSSIO
Pad ground
I/O ground
F15
D[11]
I/O
Data I/O
F16
VDDIO
Pad power
Digital I/O power, 3.3V
G1
PB[1]/PRDY[2]
I
GPIO port B / CL-PS6700 interface
signal
G2
VDDIO
Pad power
Digital I/O power, 3.3V
G3
TDO
O
JTAG data out
G4
PB[4]
I
GPIO port B
G5
PB[6]
I
GPIO port B
G6
VSSRTC
Core ground Real time clock ground
G7
VSSRTC
RTC ground Real time clock ground
G8
DD[0]
O
LCD serial display data
G9
D[3]
I/O
Data I/O
G10
VSSRTC
RTC ground Real time clock ground
G11
A[7]
O
System byte address
G12
A[8]
O
System byte address
G13
A[9]
O
System byte address
G14
VSSIO
Pad ground
I/O ground
G15
D[12]
I/O
Data I/O
G16
D[13]
I/O
Data I/O
H1
PA[7]
I
GPIO port A
H2
PA[5]
I
GPIO port A
H3
VSSIO
Pad ground
I/O ground
H4
PA[4]
I
GPIO port A
H5
PA[6]
I
GPIO port A
Table 20. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Type
Description
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