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参数资料
型号： EP7309-CV
厂商： Cirrus Logic Inc
文件页数： 26/42页
文件大小： 0K
描述： IC ARM720T MCU 74MHZ 208-LQFP
标准包装： 36
系列： EP7
核心处理器： ARM7
芯体尺寸： 32-位
速度： 74MHz
连通性： 编解码器，DAI，EBI/EMI，IrDA，键盘，SPI/Microwire1，UART/USART
外围设备： LCD，LED，MaverickKey，POR，PWM
输入/输出数： 27
程序存储器类型： ROMless
RAM 容量： 56K x 8
电压 - 电源 (Vcc/Vdd)： 2.3 V ~ 2.7 V
振荡器型： 外部
工作温度： 0°C ~ 70°C
封装/外壳： 208-LQFP
包装： 托盘
其它名称： 598-1213
32
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS507F2
EP7309
High-Performance, Low-Power System on Chip
H6
PB[0]/PRDY[1]
I
GPIO port B / CL-PS6700 interface
signal
H7
PB[2]
I
GPIO port B
H8
VSSRTC
RTC ground Real time clock ground
H9
VSSRTC
RTC ground Real time clock ground
H10
A[10]
O
System byte address
H11
A[11]
O
System byte address
H12
A[12]
O
System byte address
H13
A[13]
O
System byte address
H14
VSSIO
Pad ground
I/O ground
H15
D[14]
I/O
Data I/O
H16
D[15]
I/O
Data I/O
J1
PA[3]
I
GPIO port A
J2
PA[1]
I
GPIO port A
J3
VSSIO
Pad ground
I/O ground
J4
PA[2]
I
GPIO port A
J5
PA[0]
I
GPIO port A
J6
TXD[1]
O
UART 1 transmit data out
J7
CTS
I
UART 1 clear to send input
J8
VSSRTC
RTC ground Real time clock ground
J9
VSSRTC
RTC ground Real time clock ground
J10
A[17]
O
System byte address
J11
A[16]
O
System byte address
J12
A[15]
O
System byte address
J13
A[14]
O
System byte address
J14
nTRST
I
JTAG async reset input
J15
D[16]
I/O
Data I/O
J16
D[17]
I/O
Data I/O
K1
LEDDRV
O
IR LED drivet
K2
PHDIN
I
Photodiode input
K3
VSSIO
Pad ground
I/O ground
K4
DCD
I
UART 1 data carrier detect
K5
nTEST[1]
I
Test mode select input
K6
EINT[3]
I
External interrupt
K7
VSSRTC
RTC ground Real time clock ground
K8
ADCIN
I
SSI1 ADC serial input
K9
COL[4]
O
Keyboard scanner column drive
K10
TCLK
I
JTAG clock
K11
D[20]
I/O
Data I/O
K12
D[19]
I/O
Data I/O
K13
D[18]
I/O
Data I/O
K14
VSSIO
Pad ground
I/O ground
K15
VDDIO
Pad power
Digital I/O power, 3.3V
K16
VDDIO
Pad power
Digital I/O power, 3.3V
L1
RXD[1]
I
UART 1 receive data input
L2
DSR
I
UART 1 data set ready input
L3
VDDIO
Pad power
Digital I/O power, 3.3V
L4
nEINT[1]
I
External interrupt input
L5
PE[2]/CLKSEL
I
GPIO port E / clock input mode select
Table 20. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Type
Description
L6
VSSRTC
RTC ground Real time clock ground
L7
PD[0]/LEDFLSH
I/O
GPIO port D / LED blinker output
L8
VSSRTC
Core ground Real time clock ground
L9
COL[6]
O
Keyboard scanner column drive
L10
D[31]
I/O
Data I/O
L11
VSSRTC
RTC ground Real time clock ground
L12
A[22]
O
System byte address
L13
A[21]
O
System byte address
L14
VSSIO
Pad ground
I/O ground
L15
A[18]
O
System byte address
L16
A[19]
O
System byte address
M1
nTEST[0]
I
Test mode select input
M2
nEINT[2]
I
External interrupt input
M3
VDDIO
Pad power
Digital I/O power, 3.3V
M4
PE[0]/BOOTSEL[0]
I
GPIO port E / Boot mode select
M5
TMS
I
JTAG mode select
M6
VDDIO
Pad power
Digital I/O power, 3.3V
M7
SSITXFR
I/O
DAI/CODEC/SSI2 frame sync
M8
DRIVE[1]
I/O
PWM drive output
M9
FB[0]
I
PWM feedback input
M10
COL[0]
O
Keyboard scanner column drive
M11
D[27]
I/O
Data I/O
M12
VSSIO
Pad ground
I/O ground
M13
A[23]
O
System byte address
M14
VDDIO
Pad power
Digital I/O power, 3.3V
M15
A[20]
O
System byte address
M16
D[21]
I/O
Data I/O
N1
nEXTFIQ
I
External fast interrupt input
N2
PE[1]/BOOTSEL[1]
I
GPIO port E / boot mode select
N3
VSSIO
Pad ground
I/O ground
N4
VDDIO
Pad power
Digital I/O power, 3.3V
N5
PD[5]
I/O
GPIO port D
N6
PD[2]
I/O
GPIO port D
N7
SSIRXDA
I/O
DAI/CODEC/SSI2 serial data input
N8
ADCCLK
O
SSI1 ADC serial clock
N9
SMPCLK
O
SSI1 ADC sample clock
N10
COL[2]
O
Keyboard scanner column drive
N11
D[29]
I/O
Data I/O
N12
D[26]
I/O
Data I/O
N13
HALFWORD
O
Halfword access select output
N14
VSSIO
Pad ground
I/O ground
N15
D[22]
I/O
Data I/O
N16
D[23]
I/O
Data I/O
P1
VSSRTC
RTC ground Real time clock ground
P2
RTCOUT
O
Real time clock oscillator output
P3
VSSIO
Pad ground
I/O ground
P4
VSSIO
Pad ground
I/O ground
P5
VDDIO
Pad power
Digital I/O power, 3.3V
Table 20. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Type
Description
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