参数资料
| 型号： | EP9315-IBZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 43/106页 |
| 文件大小： | 0K |
| 描述： | IC ARM9 SOC ENH UNIV 352PBGA |
| 标准包装： | 40 |
| 系列： | EP9 |
| 核心处理器： | ARM9 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 200MHz |
| 连通性： | EBI/EMI，EIDE，以太网，I²C，IrDA，键盘/触摸屏，PCMCIA，SPI，UART/USART，USB |
| 外围设备： | AC'97，DMA，I²S，LCD，LED，MaverickKey，POR，PWM，WDT |
| 输入/输出数： | 16 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 32K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.65 V ~ 3.6 V |
| 数据转换器： | A/D 8x12b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 352-BGA |
| 包装： | 托盘 |
| 配用： | 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9 |
| 其它名称： | 598-1263 |
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DS785UM1
2-3
Copyright 2007 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2
A 16 kbyte instruction and a 16 kbyte data cache are included to increase performance for
cache-enabled memory regions. The 64-way associative cache also has lock-down
capability. A 16-word Write Buffer allows cached instructions to be fetched and decoded while
the Write Buffer sends data to external memory.
The ARM920T Core supports a number of co-processors, including the MaverickCrunch co-
processor by means of a specific pipeline architecture interface.
2.2.3.1 ARM9TDMI Core
ARM9TDMI core is responsible for executing both 32-bit ARM and 16-bit Thumb instructions.
Each provides a unique advantage to a system design. Internally, the instructions enter a 5-
stage pipeline. These stages are:
Instruction Fetch
Instruction Decode
Execute
Data Memory Access
Register Write
All instructions are fully interlocked. This mechanism will delay the execution stage of a
instruction if data in that instruction comes from a previous instruction that is not available yet.
This simply insures that software will function identically across different implementations.
For memory access instructions, the base register used for the access will be restored by the
ARM Core in the event of an Abort exception. The base register will be restored to the value
contained in it immediately before execution of the instruction.
The ARM9TDMI core memory interface includes a separate instruction and data interface to
allow concurrent access of instructions and data to reduce the number of CPI (cycles per
instruction). Both interfaces use pipeline addressing. The core can operate in big and little
endian mode. Endianess affects both the address and the data interfaces.
The memory interface executes four types of memory transfers: sequential, non-sequential,
internal, and co-processor. It will also support uni- and bi-directional transfer modes.
The core provides a debug interface called JTAG (Joint Testing Action Group). This interface
provides debug capability with five external control signals:
TDO - Test Data Out
TDI - Test Data In
TMS - Test Mode Select
TCK - Test Clock
nTRST - Test Reset
There are six scan chains (0 through 5) in the ARM9TDMI controlled by the JTAG Test
Access Port (TAP) controller. Details on the individual scan chain function and bit order can
be found in the ARM920T Technical Reference Manual.
相关PDF资料 |
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